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| Number | Title | Issue Date |
| 8156310 | Method and apparatus for data stream alignment support One embodiment of the present method and apparatus for data stream alignment support includes retrieving a first input from a first register file, retrieving a second input from a second register file, the second register file being dedicated to a stream shift unit ... | 04/10/2012 |
| 8103852 | Information handling system including a processor with a bifurcated issue queue An information handling system includes a processor with a bifurcated unified issue queue that may perform unified issue queue VSU store instruction dependency operations. The bifurcated unified issue queue BUIQ maintains VSU store instructions in the form of intern... | 01/24/2012 |
| 8074051 | Multithreaded processor with multiple concurrent pipelines per thread A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded pr... | 12/06/2011 |
| 8065502 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices a... | 11/22/2011 |
| 7877573 | Work-efficient parallel prefix sum algorithm for graphics processing units One embodiment of the present invention sets forth a technique for computing a parallel prefix sum using one or more cooperative thread arrays (CTA) within a graphics processing unit. The prefix sum input list is partitioned and distributed to each CTA. Within each ... | 01/25/2011 |
| 7809925 | Processing unit incorporating vectorizable execution unit A vectorizable execution unit is capable of being operated in a plurality of modes, with the processing lanes in the vectorizable execution unit grouped into different combinations of logical execution units in different modes. By doing so, processing lanes can be s... | 10/05/2010 |
| 7779229 | Method and arrangement for bringing together data on parallel data paths A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various process... | 08/17/2010 |
| 7681013 | Method for variable length decoding using multiple configurable look-up tables Methods and apparatuses for variable length decoding using multiple look-up tables simultaneously. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a string of bits; generati... | 03/16/2010 |
| 7627735 | Implementing vector memory operations In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector memory operation, and a controller to generate an output slice from one o... | 12/01/2009 |
| 7475222 | Multi-threaded processor having compound instruction and operation formats A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded instructions. One or more of the instructions are in a compound instruction forma... | 01/06/2009 |
| 7437544 | Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processin... | 10/14/2008 |
| 7434040 | Copying of unaligned data in a pipelined operation Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16 bytes of data from an unaligned data area to an aligned data area during... | 10/07/2008 |
| 7404065 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instructio... | 07/22/2008 |
| 7360064 | Thread interleaving in a multithreaded embedded processor The present invention provides a network multithreaded processor, such as a network processor, including a thread interleaver that implements fine-grained thread decisions to avoid underutilization of instruction execution resources in spite of large communication l... | 04/15/2008 |
| 7350036 | Technique to perform concurrent updates to a shared data structure A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distribu... | 03/25/2008 |
| 7305649 | Automatic generation of a streaming processor circuit A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of cir... | 12/04/2007 |
| 7302627 | Apparatus for efficient LFSR calculation in a SIMD processor The apparatus provides for efficient implementation of multiple-bit leap-forward LFSRu calculation in a SIMD processor. This provides an accelerated and programmable way to implement LFSR calculations in a SAID processor. Conditional vector exclusive-OR accumulation... | 11/27/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7290122 | Dataflow graph compression for power reduction in a vector processor A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. T... | 10/30/2007 |
| 7284113 | Synchronous periodical orthogonal data converter An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate corresponding vector components of the sequential vector component flow... | 10/16/2007 |
| 7272704 | Hardware looping mechanism and method for efficient execution of discontinuity instructions A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or superscalar processor. For example, the hardware looping mechanism may ... | 09/18/2007 |
| 7257695 | Register file regions for a processing system According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information ... | 08/14/2007 |
| 7257665 | Branch-aware FIFO for interprocessor data sharing A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to... | 08/14/2007 |
| 7219213 | Flag bits evaluation for multiple vector SIMD channels execution According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by th... | 05/15/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7206857 | Method and apparatus for a network processor having an architecture that supports burst writes and/or reads A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The ... | 04/17/2007 |
| 7206920 | Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to th... | 04/17/2007 |
| 7200724 | Two dimensional data access in a processor A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specify... | 04/03/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7194609 | Branch reconfigurable systems and methods The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the plurality of processing elements generates a branch command. The invention uses a programmable network that tr... | 03/20/2007 |
| 7191432 | High frequency compound instruction mechanism and method for a compare operation in an arithmetic logic unit A high-frequency compound instruction mechanism and method allows performing a common compare immediate function before an add function has completed, thereby reducing the number of cycles to perform the add-compare function. By increasing the speed of performing th... | 03/13/2007 |
| 7174047 | Single-instruction multiple-data (SIMD)-based algorithms for processing video data In a video encoder/decoder, a method processes a discrete cosine transform (DCT) block of coefficients. The method receives a DCT block of coefficients, and linearizes the DCT block of coefficients into a one dimensional array of sequentially arranged coefficients. ... | 02/06/2007 |
| 7167514 | Processing of quinary data A FIR filter in a Gigabit transceiver in which data words are represented in three bits: SIGN representing word sign, SHIFT representing requirement for a shift operation, and ZERO indicating whether the word is zero. An AND gate ANDs an input coefficient and the ZE... | 01/23/2007 |
| 7159100 | Method for providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector regis... | 01/02/2007 |
| 7146489 | Methods for intelligent caching in an embedded DRAM-DSP architecture An efficient embedded-DRAM processor architecture and associated methods. In one exemplary embodiment, the architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-ad... | 12/05/2006 |
| 7113545 | Method and apparatus for motion compensated temporal interpolation of video sequences A method and device for processing video signals is provided, comprising the steps of: selecting a motion vector having the least mean square error from an M×N block, applying a vector filter to the motion vector, and if filter output MSE is below a present thresho... | 09/26/2006 |
| 7110431 | Hardware and software for performing computations in a short-code spread-spectrum communications system The invention provides methods and apparatus for multiple user detection (MUD) processing that have application, for example, in improving the capacity CDMA and other wireless base stations. One aspect of the invention provides a multiprocessor, multiuser detection ... | 09/19/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7100026 | System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be proce... | 08/29/2006 |
| 7100019 | Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface. An address calculator includes a set of storage elements, such as reg... | 08/29/2006 |
