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| Number | Title | Issue Date |
| 7529907 | Method and apparatus for improved computer load and store operations Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register ... | 05/05/2009 |
| 7467288 | Vector register file with arbitrary vector addressing A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a plurality of storage elements for storing data elements of the data v... | 12/16/2008 |
| 7428628 | Method and apparatus for management of control flow in a SIMD device A single instruction multiple data processing device includes a plurality of processing elements. Each processing element includes an execute mask count register storing a plurality of bits. The writing updated data to registers in each processing element is enabled... | 09/23/2008 |
| 7404065 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instructio... | 07/22/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7302627 | Apparatus for efficient LFSR calculation in a SIMD processor The apparatus provides for efficient implementation of multiple-bit leap-forward LFSRu calculation in a SIMD processor. This provides an accelerated and programmable way to implement LFSR calculations in a SAID processor. Conditional vector exclusive-OR accumulation... | 11/27/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7219213 | Flag bits evaluation for multiple vector SIMD channels execution According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by th... | 05/15/2007 |
| 7206920 | Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in elements of a second register, which includes N elements corresponding to th... | 04/17/2007 |
| 7177974 | Data processing device with a memory location in which data is stored according to a WOM (write once memory) code A device contains a memory that stores a WOM codeword that encodes successive generations of data values. When the codeword must be updated to represent a new data value, the device determines which updates of the dataword can be realized by feasible single bit upda... | 02/13/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7127593 | Conditional execution with multiple destination stores A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine a... | 10/24/2006 |
| 7120781 | General purpose register file architecture for aligned simd A register file architecture in a general purpose digital signal processor (DSP) supports alignment independent SIMD (Single Instruction/Multiple Data) operations. The register file architecture includes a register pair and an alignment multiplexer. Two 32 bit group... | 10/10/2006 |
| 7100026 | System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be proce... | 08/29/2006 |
| 7093102 | Code sequence for vector gather and scatter Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required complex address calculation hardware and other hardware to perform vector ... | 08/15/2006 |
| 7076639 | Apparatus and method for masked move to and from flags register in a processor A method and apparatus are provided for writing to a flags register in a pipeline microprocessor. Responsive to a macro instruction that directs a write to the flags register, a mask is generated using destination information for the write and privilege level inform... | 07/11/2006 |
| 7058794 | Apparatus and method for masked move to and from flags register in a processor A method and apparatus are provided for storing a flags register in a processor. In response to a macro instruction directing the store operation, such as a push flags macro instruction, a mask is generated using privilege level information (i.e., current operating ... | 06/06/2006 |
| 7047393 | Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a targ... | 05/16/2006 |
| 7028171 | Multi-way select instructions using accumulated condition codes The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes ... | 04/11/2006 |
| 7003653 | Method for rapid interpretation of results returned by a parallel compare instruction A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied t... | 02/21/2006 |
| 7000099 | Large table vectorized lookup by selecting entries of vectors resulting from permute operations on sub-tables A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 02/14/2006 |
| 6973404 | Method and apparatus for administering inversion property in a memory tester A method and apparatus permits use of a tester memory (31) as storage for an inversion mask. The inversion mask indicates to the tester which cells in a DUT memory (14) are logically inverted during testing. Data information and the inverse of the data... | 12/06/2005 |
| 6958718 | Table lookup operation within a data processing system A table lookup extension instruction is provided in which index values stored within an index register D2 are used to select data elements stored within one or more table registers D0, D1 for storage into corresponding positions within a result ... | 10/25/2005 |
| 6931511 | Parallel vector table look-up with replicated index element vector Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector of indices includes: generating a second vector of indices in a vector... | 08/16/2005 |
| 6922764 | Memory, processor system and method for performing write operations on a memory region A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask signal which is assigned to the data bundle. The memory also has a unit... | 07/26/2005 |
| 6922771 | Vector floating point unit The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor coupled, a floating point multiplier, and a floating point adder. Th... | 07/26/2005 |
| 6918029 | Method and system for executing conditional instructions using a test register address that points to a test register from which a test code is selected A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length which identifie... | 07/12/2005 |
| 6904510 | Data processor having a respective multiplexer for each particular field A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is controlled by condition data for a particular field, preferably from an ... | 06/07/2005 |
| 6865517 | Aggregation of sensory data for distributed decision-making A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being connected by a communications facility acquiring local data from the ... | 03/08/2005 |
| 6789180 | Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to control access to the memory device. Each of the control circuits may be c... | 09/07/2004 |
| 6691308 | Method and apparatus for changing microcode to be executed in a processor A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In t... | 02/10/2004 |
| 6560698 | Register change summary resource A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks... | 05/06/2003 |
| 6530015 | Accessing a test condition for multiple sub-operations using a test register A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also contains an address field of a predetermined bit length whic... | 03/04/2003 |
| 6530011 | Method and apparatus for vector register with scalar values A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and memories, is capable of identifying a first data in a first scalar... | 03/04/2003 |
| 6496916 | System for flexible memory paging in partitioning memory A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one software application program. The bits of the memory paging ma... | 12/17/2002 |
| 6324638 | Processor having vector processing capability and method for executing a vector instruction in a processor A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a... | 11/27/2001 |
| 6308250 | Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence... | 10/23/2001 |
| 6298431 | Banked shadowed register file An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.... | 10/02/2001 |
| 6269435 | System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processe... | 07/31/2001 |
| 6266759 | Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor A vector-processor SIMD RISC computer system uses virtual addressing and overlapped instruction execution. Indicators for each of the architected registers assume different states when an instruction, overlapped with a vector memory-reference instruction,... | 07/24/2001 |
