Bizarre Patents
Pneumatic Shoe Lacing Apparatus
This invention provides a pneumatic shoe lacing apparatus for the pneumatic lacing of shoe.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5598546 | Dual-architecture super-scalar pipeline A dual-instruction-set processor processes instructions from two or more instruction sets. The processor has several pipelines for processing different types of operations--Memory, ALU, and Branch operations. Instructions are decoded by RISC and CISC inst... | 01/28/1997 |
| 5590364 | Signal processing apparatus In a signal processing apparatus which stores a program inside, and performs a series of processes on a received signal according to the program, such as an arithmetic operation or a delay process, and outputs the processed signal, for rewriting the progr... | 12/31/1996 |
| 5590368 | Method and apparatus for dynamically expanding the pipeline of a microprocessor A dynamically expandable pipeline in a microprocessor. The present invention is used in a microprocessor or a microprocessor in a computer system. The present invention delays execution of a cacheable LOAD instruction by a bus controller for one cycle to ... | 12/31/1996 |
| 5581779 | Multiple chip processor architecture with memory interface control register for in-system programming An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and be... | 12/03/1996 |
| 5574932 | One-chip microcomputer and program development/evaluation system therefor A one-chip microcomputer having a mode setting circuit 40a in a first MCU 1a and a second MCU 1b for setting either a first evaluation operation mode under which the operations of memory 3a stops and programs and data are read from the outside via termina... | 11/12/1996 |
| 5539896 | Method and apparatus for dynamically linking code segments in real time in a multiprocessor computing system employing dual buffered shared memory A system is provided including a host processor and an audio capture and playback adapter having a DSP co-processor. The adapter includes shared memory accessible from both the DSP and the host. A DSP program is periodically written to the shared memory b... | 07/23/1996 |
| 5530804 | Superscalar processor with plural pipelined execution units each unit selectively having both normal and debug modes A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referre... | 06/25/1996 |
| 5517661 | Single-chip micro-computer having a plurality of operation modes Disclosed are a single-chip micro-computer optimized for an electronic memorandum book, an electronic dictionary or the like by suppressing the increase of the number of terminals, and an electronic apparatus having therein the single-chip micro-computer.... | 05/14/1996 |
| 5515517 | Data processing device with test circuit A data processing device with a test circuit has a plurality of macro blocks, a common bus for transferring the output of one of the macro blocks to the other macro blocks, and a tri-state buffer incorporated into each macro block. A bus control circuit s... | 05/07/1996 |
| 5509139 | Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting ... | 04/16/1996 |
| 5506994 | Multiprocessor-type one-chip microcomputer with dual-mode functional terminals A multiprocessor-type one-chip microcomputer, of the type having a plurality of processors, each having a separate address space, a plurality of programmable ROMs, for storing program data for each processor, and a set of functional terminals, with the mi... | 04/09/1996 |
| 5483659 | Apparatus for controlling a signal processing system to operate in high and low speed modes In an apparatus for controlling a signal processing system to operate in high and low speed modes, a control unit determines a speed of system clock signals in accordance with the interpretation of a program when external clock signals are received. When ... | 01/09/1996 |
| 5479652 | Microprocessor with an external command mode for diagnosis and debugging A microprocessor is disclosed herein having an external command mode for directly accessing the execution unit, responsive to externally generated commands and instructions. An external instruction path is provided, as well as a conventional processor-dri... | 12/26/1995 |
| 5475852 | Microprocessor implementing single-step or sequential microcode execution while in test mode A microprocessor having a test mode wherein a test instruction including an instruction for executing the whole microprogram routine and a step-execution instruction for executing only one microinstruction of an arbitrary address in a micro ROM for easily... | 12/12/1995 |
| 5463760 | Break function in-circuit emulator for a microprocessor with a cache memory An in-circuit emulator comprising a microprocessor having an input terminal for selecting whether or not the data obtained by accessing an external address should be registered in the cache memory, a register for storing an address for discontinuing the e... | 10/31/1995 |
| 5438672 | Microcontroller emulator for plural device architecture configured by mode control data and operated under control code transmitted via same switching bus A configurable emulator system for emulating a microcontroller device architecture selected from a plurality of microcontroller device architectures is provided. The configurable emulator includes a master microcontroller emulator comprising at least one ... | 08/01/1995 |
| 5392420 | In circuit emulator(ICE) that flags events occuring in system management mode(SMM) A micro processor emulator in which an SMM flag is set whenever a processor being emulated enters system management mode (SMM) mode, a diminished power mode, and is reset when the processor leaves SMM mode. Events, such as branch instructions, that are re... | 02/21/1995 |
| 5386579 | Minimum pin-count multiplexed address/data bus with byte enable and burst address counter support microprocessor transmitting byte enable signals on multiplexed address/data bus having burst address counter for supporting signal datum and burst transfer A multiplexed address and data bus system provides a minimum pin count with byte enable and burst address counter support. The partitioning of the address bus includes separate byte enables to indicate specifically which bytes of the word are being access... | 01/31/1995 |
| 5361374 | Integrated data processor having mode control register for controlling operation mode of serial communication unit A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two sorts of control procedures among HDLC procedu... | 11/01/1994 |
| 5321842 | Three-state driver with feedback-controlled switching A processor specially adapted for use as a coprocessor. The processor is implemented as a microprocessor. The adaptations include the following: The microprocessor has a master-slave pin which receives an input which determines whether the microprocessor ... | 06/14/1994 |
| 5303383 | Multiprocessor computer system A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network ... | 04/12/1994 |
| 5291197 | One-chip data processor with built-in A/D converter for automatically repeating A/D conversions without instructions from a CPU A data processing unit according to the present invention has a central processing unit, and an analog-to-digital converter circuit associated with a plurality of input nodes respectively supplied with analog signals. The analog-to-digital converter circu... | 03/01/1994 |
| 5280593 | Computer system permitting switching between architected and interpretation instructions in a pipeline by enabling pipeline drain A hardware controlled pipelined processor having an interpretive storage and multiple execution units employs interpretive storage "milli-instructions" and an interpretive execution "milli-mode". Additional hardware controlled instructions that are exclus... | 01/18/1994 |
| 5218712 | Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the ... | 06/08/1993 |
| 5142688 | Data processor test mode access method A data processor has a test mode which may be selectively accessed for either production testing of the processor or user testing from an external control signal. To enter the test mode, both an external signal applied to an integrated circuit package pin... | 08/25/1992 |
| 5133057 | Co-processor for control setting an internal flag register operation mode which controlled a main processor execution mode in a multi-processor system A multiprocessor system which includes a non-conventional co-processor to make it easier to observe the internal state of the co-processor. The system consists of a main processor, a co-processor, and a main memory unit connected by an external bus. The m... | 07/21/1992 |
| 5101498 | Pin selectable multi-mode processor A processor which has two different communications modes, a test mode, an an emulator mode is shown. These modes are selected by controlling inputs to two pins. More modes could be added with more pins. When a given mode is switched into, certain I/O pins... | 03/31/1992 |
| 4956800 | Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus A first processor outputs a series of macro instruction steps which are obtained by dividing an executing sequence of instructions to specify arithmetic operating processes to proper executing units and to time-sequentially output a macro instruction to i... | 09/11/1990 |
| 4930067 | Microcomputer having a high-speed operation mode and a low-speed operation mode with intermittent disabling of sense amplifiers A microcomputer has an instruction memory and a high-speed sense amplifier and can selectively operate according to a high-speed operation mode and to a low-speed operation mode. The high-speed sense amplifier is activated in a full time or with a large d... | 05/29/1990 |
| 4839851 | Programmable data path device A programmable data path device capable of operating as a general purpose hardware accelerator. The device includes a plurality of processing cells, memory such as RAM or EPROM for storing data path control words, and an address module for sequentially pr... | 06/13/1989 |
| 4799144 | Multi-function communication board for expanding the versatility of a computer A single board multiple option card for expanding the versatility of a host computer includes an onboard microprocessor, a digital signal processor and a switched memory device. The switched memory is accessible by the onboard microprocessor and the digit... | 01/17/1989 |
| 4780820 | Control flow computer using mode and node driving registers for dynamically switching between parallel processing and emulation of von neuman processors A parallel processing computer comprises at least a memory for storing program as well as data and instructions for executing the program, a plurality of functional units, a node driving register for indicating executable instructions which are allowed to... | 10/25/1988 |
| 4777590 | Portable computer A computer system has a system bus with several sockets or slots therein which receive memory modules. Each module can be used to implement at least one of a variety of functions. The functions include operating system programs, application programs, and ... | 10/11/1988 |
| 4497021 | Microcomputer system operating in multiple modes A microcomputer system having a central processing unit (CPU) responsive to mode control signals for operating the system in respective operating modes, a power supply circuit for supplying a reset signal to the CPU, a memory, and a keyboard, is provided ... | 01/29/1985 |
| 4450519 | Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories A single-chip microprocessor device of the MOS/LSI type contains an ALU, several internal busses, a number of address/data registers, and an instruction register (IR) with associated control decode or microcontrol generator circuitry. The device communica... | 05/22/1984 |
| 4441154 | Self-emulator microcomputer An electronic digital processor system including an internal memory, an arithmetic and logic unit, registers, peripheral control circuitry providing an internal mode, an external mode, emulator mode, data paths, and control and timing circuitry. In the in... | 04/03/1984 |
| 4412283 | High performance microprocessor system A microprocessor comprising: an address data path; an arithmetic logic unit data path, said data paths being capable of simultaneous operation; an information bus; a shared bus register; a shared input multiplexing apparatus for selectively transferring a... | 10/25/1983 |
| 3988717 | General purpose computer or logic chip and system A general purpose logic chip may be replicated for use to construct both the arithmetic unit and the control sections of a computer or other digital data processing or logic circuitry. The chip includes a number of features which when taken together permi... | 10/26/1976 |
