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| Number | Title | Issue Date |
| 7664931 | Scalable and configurable multimedia system for a vehicle A scalable and fully configurable computing architecture for a mobile multimedia architecture used in a vehicle includes a head unit having a processor, a field programmable gate array and a memory. The processor and the memory are configured to communicate over a f... | 02/16/2010 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7443885 | CAN device featuring advanced can filtering and message acceptance A device that supports a plurality n of message objects, including a plurality of registers associated with each message object, including at least one object match ID register that contains a multi-bit object match ID field, and at least one object mask register th... | 10/28/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7318090 | Method for utilizing concurrent context switching to support isochronous processes A method for utilizing concurrent context switching to support isochronous processes preferably comprises a main context that is configured to support system execution tasks, a first concurrent context that supports a first set of concurrent execution and loading pr... | 01/08/2008 |
| 7315937 | Microprocessor instructions for efficient bit stream extractions A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instructio... | 01/01/2008 |
| 7315933 | Re-configurable circuit and configuration switching method The present invention is a re-configurable circuit capable of reducing latency by selecting a route for skipping the FF of an operation unit and outputting data to a connection destination operation unit if an accumulated process time is below an operation cycle all... | 01/01/2008 |
| 7315935 | Apparatus and method for port arbitration in a register file on the basis of functional unit issue slots A microprocessor is configured to provide port arbitration in a register file. The microprocessor includes a plurality of functional units configured to collectively operate on a maximum number of operands in a given execution cycle, and a register file providing a ... | 01/01/2008 |
| 7304883 | Semiconductor integrated circuit In a semiconductor integrated circuit having a register file of a multiport configuration, a first holding circuit 20A is dedicated to a first functional block having one first write port section 21AW and two first read port sections 21AR1 | 12/04/2007 |
| 7302399 | Method and system for processing travel reservation data One aspect of the invention is a travel pricing system comprising a data store and a server coupled to the data store. The server is operable to receive new reservation data that conflicts with old reservation data in the data store. The new reservation data compris... | 11/27/2007 |
| 7281110 | Random access memory controller with out of order execution A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge... | 10/09/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7260668 | Network co-processor for vehicles A network processor exchanges data of various descriptions via a plurality of network nodes with external network devices, such as other processors, controllers, transducers, or sensors. The network processor includes a master processor for control tasks of the proc... | 08/21/2007 |
| 7257084 | Rollover bits for packet departure time calculator A traffic management processor includes a departure time calculator for generating a departure time for each packet, a departure time table having a plurality of rows, each having a first portion for storing the departure time for a corresponding packet and having a... | 08/14/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7245818 | Moving image reproducing apparatus A moving image reproducing apparatus includes a CPU mounted with a real-time OS. When a set key is pressed, the CPU executes concurrently a transfer process of compressed image data and sound data from a magneto-optical disk to an SDRAM and a reproduce process of co... | 07/17/2007 |
| 7231552 | Method and apparatus for independent control of devices under test connected in parallel A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TA... | 06/12/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7206924 | Microcontroller instruction set A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is... | 04/17/2007 |
| 7203818 | Microcontroller instruction set A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is... | 04/10/2007 |
| 7200060 | Memory driver architecture and associated methods A memory driver architecture and associated methods are generally described. ... | 04/03/2007 |
| 7197577 | Autonomic input/output scheduler selector The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to ... | 03/27/2007 |
| 7191440 | Tracking operating system process and thread execution and virtual machine execution in hardware or in a virtual machine monitor Transitions among schedulable entities executing in a computer system are tracked in computer hardware or in a virtual machine monitor. In one aspect, the schedulable entities are operating system processes and threads, virtual machines, and instruction streams exec... | 03/13/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7139003 | Methods of processing graphics data including reading and writing buffers Apparatuses and methods for detecting position conflicts during fragment processing are described. Prior to executing a program on a fragment, a conflict detection unit, within a fragment processor checks if there is a position conflict indicating a RAW (read after ... | 11/21/2006 |
| 7137110 | Profiling ranges of execution of a computer program Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a p... | 11/14/2006 |
| 7124327 | Control over faults occurring during the operation of guest software in the virtual-machine architecture In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more filtering criterion. If the determination is positive, co... | 10/17/2006 |
| 7123651 | Adaptable hybrid and selection method for ADSL modem data rate improvement A method of operating a modem generally comprising the steps of (A) transmitting an invalid signal from the modem at each of a plurality of settings for an echo cancelling hybrid of the modem, (B) calculating a plurality of merit values each in response to an echo s... | 10/17/2006 |
| 7120715 | Priority arbitration based on current task and MMU A digital system and method of operation is provided in which several processors (740(0)–740(n)) are connected to a shared resource (750). Each processor has an access priority register (1410) that is loaded with an access priori... | 10/10/2006 |
| 7111290 | Profiling program execution to identify frequently-executed portions and to assist binary translation A method and a computer with circuitry configured for performance of the method are disclosed. During a profiled interval of an execution of a program on a computer, profile information is recorded describing the execution, without the program having been compiled f... | 09/19/2006 |
| 7111287 | Global processor resource assignment in an assembler An assembler for assembling code is disclosed. The assembly language code includes a plurality of code blocks associated with resource-needs, such as variables, and resources, such as registers, I/O locations, memory locations, and coprocessors. A technology is prov... | 09/19/2006 |
| 7099818 | System and method for automatically matching components in a debugging system Communications between a device and a debugging system are effectuated by programming an ICE with a first logic set, which enables the ICE to establish communications with the device and determine a unique identifier thereof. The ICE communicates the device's unique... | 08/29/2006 |
| 7096297 | System and method for delaying an interrupt request until corresponding data is provided to a destination device A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from ... | 08/22/2006 |
| 7095342 | Compressing microcode In one embodiment, the present invention includes a method to compress data stored in a memory to reduce size and power consumption. The method includes segmenting each word of a code portion into multiple fields, forming tables having unique entries for each of the... | 08/22/2006 |
| 7093094 | Random access memory controller with out of order execution A memory controller for a multi-bank random access memory (RAM) such as SDRAM includes a transaction slicer for slicing complex client transactions into simple slices, and a command scheduler for re-ordering preparatory memory commands such as activate and precharge... | 08/15/2006 |
| 7069421 | Side tables annotating an instruction stream A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address r... | 06/27/2006 |
| 7065633 | System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may ... | 06/20/2006 |
| 7047392 | Data processing apparatus and method for controlling staged multi-pipeline processing A data processing apparatus that reduces a fanout load of a control signal for controlling a pipeline includes a first pipeline processing portion for executing a processing in five divided stages, a second pipeline processing portion for executing a processing one ... | 05/16/2006 |
| 7047394 | Computer for execution of RISC and CISC instruction sets A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction s... | 05/16/2006 |
| 7020789 | Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a... | 03/28/2006 |
