Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8117424 | Systems, devices, and/or methods for managing programmable logic controller processing Certain exemplary embodiments can provide a programmable logic controller, which can comprise a Reduced Instruction Set Computer (RISC) processor. The RISC processor can be adapted to, responsive to a received request to process a Boolean operation, execute a single... | 02/14/2012 |
| 8112615 | Single cycle reduced complexity CPU A single cycle RISC CPU. The single cycle RISC CPU includes an instruction decoder configured to perform an instruction fetch and an instruction decode. An arithmetic logic unit is coupled to the instruction decoder. The arithmetic logic unit is configured to perfor... | 02/07/2012 |
| 7620796 | System and method for acceleration of streams of dependent instructions within a microprocessor A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is ... | 11/17/2009 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7373369 | Advanced execution of extended floating-point add operations in a narrow dataflow A method and system for performing floating point additive arithmetic operations of long operands in a narrow dataflow. The operands include first and second floating point numbers having first and second mantissas, respectively, the second operand greater than the ... | 05/13/2008 |
| 7366876 | Efficient emulation instruction dispatch based on instruction width In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines... | 04/29/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7360011 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics-for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage, ... | 04/15/2008 |
| 7337443 | Method and apparatus for processing program threads A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is annotated with the results of the benchmarking of the program image. Basi... | 02/26/2008 |
| 7328313 | Methods to perform cache coherency in multiprocessor system using reserve signals and control bits A cache controller prevents the use of data in a write-back cache memory from being propagated except to a client asserting a reserve signal, if a first control bit is set, or until the data is backed-up in a main memory, if a second control bit is set. The control ... | 02/05/2008 |
| 7320125 | Program execution stack signatures A digital computer call stack or combined call stack and data stack is traced and analyzed following the occurrence of an unhandled exception or crash. Stack frame sizes and other artifacts are used to form a distinctive stack signature that generally reflects execu... | 01/15/2008 |
| 7315764 | Integrated circuit, method, and computer program product for recording and reproducing digital data An integrated circuit to control a media player/recorder having a wireless receiver, a storage device, and an output circuit, wherein the wireless receiver receives a signal representing encoded media data, and a method and computer program product for same. It comp... | 01/01/2008 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7302557 | Method and apparatus for modulo scheduled loop execution in a processor architecture A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prol... | 11/27/2007 |
| 7287148 | Unified shared pipeline allowing deactivation of RISC/DSP units for power saving An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and t... | 10/23/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7269713 | Adjusting thread instruction issue rate based on deviation of actual executed number from intended rate cumulative number A method and apparatus for controlling issue rate of instructions for an instruction thread to be executed by a processor is provided. The rate at which instructions are to be executed for an instruction thread are stored (46) and requests are issued (44 | 09/11/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7254720 | Precise exit logic for removal of security overlay of instruction space A circuit generally comprising a first memory, a processor and a logic block is disclosed. The first memory may store (i) a write instruction to store a non-highest security value of at least three security values in a register and (ii) a jump instruction to a secon... | 08/07/2007 |
| 7251720 | Flexible digital signal processor The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system. The digital signal processor is a flexible digital signal processor and comprises... | 07/31/2007 |
| 7243214 | Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of s... | 07/10/2007 |
| 7228402 | Predicate register file write by an instruction with a pending instruction having data dependency A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data de... | 06/05/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7225436 | Java hardware accelerator using microcode engine A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™... | 05/29/2007 |
| 7216196 | Memory hub and method for memory system performance monitoring A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, number or percentage of prefetch hits, cache hit rate or percentage... | 05/08/2007 |
| 7210059 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 04/24/2007 |
| 7210027 | Processor transferring multiple working register windows transfers global registers only for select exception handling In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global register... | 04/24/2007 |
| 7207032 | Expanding a software program by insertion of statements Every function that is called (“called function”) is expanded by insertion of several statements at the entry and exit thereof. Moreover, a calling function may also be expanded, by insertion of statements prior to and/or subsequent to a statement in which a cal... | 04/17/2007 |
| 7200735 | High-performance hybrid processor with configurable execution units A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and... | 04/03/2007 |
| 7194601 | Low-power decode circuitry and method for a processor having multiple decoders A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes se... | 03/20/2007 |
| 7185329 | Use of different color sequences for variables of different sizes and different semantics Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments,... | 02/27/2007 |
| 7185262 | Method and device for monitoring a data processing and transmission Data processing and transmission is monitored in a data processing unit. The data processing unit has a plurality of software modules, between which data is exchanged, a check sum is allocated to the data of a data transmission, which, in selected software modules i... | 02/27/2007 |
| 7171546 | CPU life-extension apparatus and method A CPU life-extension apparatus and method makes a processor appear to be an upgraded CPU to substantially all software applications accessed thereby, thereby reducing the need and expense of upgrading a selected processor. A CPU life-extension module translates new ... | 01/30/2007 |
| 7171547 | Method and apparatus to save processor architectural state for later process resumption A method and an apparatus for restoring logic states using programming code are disclosed. In one embodiment, the process of a data processing system identifies a first logic value stored in a first register and branches to a first location within the programming co... | 01/30/2007 |
| 7162621 | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 01/09/2007 |
| 7159099 | Streaming vector processor with reconfigurable interconnection switch A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch... | 01/02/2007 |
| 7137045 | Decoding method and apparatus therefor A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some c... | 11/14/2006 |
