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| Number | Title | Issue Date |
| 7937560 | Processor pipeline architecture logic state retention systems and methods A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to s... | 05/03/2011 |
| 7882334 | Processor pipeline architecture logic state retention systems and methods A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the co... | 02/01/2011 |
| 7441100 | Processor synchronization in a multi-processor computer system A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a lead processor of the plurality of processors when the lead processor... | 10/21/2008 |
| 7437521 | Multistream processing memory-and barrier-synchronization method and apparatus A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects o... | 10/14/2008 |
| 7421384 | Semiconductor integrated circuit device and microcomputer development supporting device During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits i... | 09/02/2008 |
| 7343279 | Universal approach for simulating, emulating, and testing a variety of serial bus types An electronic apparatus for testing equipment for serial busses employs a generic bus model that breaks down a serial bus into separate layers that are managed by separate processors. The processors have parameters that can be programmed for communicating via one ty... | 03/11/2008 |
| 7334114 | Real-time monitoring, alignment, and translation of CPU stalls or events A system and method of tracing a group of processor events in real-time in order to enable a programmer to debug and profile the operation and execution of code on the processor. This may be accomplished by running one or more traces on the same or different groups ... | 02/19/2008 |
| 7302551 | Suppression of store checking An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruc... | 11/27/2007 |
| 7280539 | Data driven type information processing apparatus In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a funct... | 10/09/2007 |
| 7243212 | Processor-controller interface for non-lock step operation Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not... | 07/10/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7200736 | Method and system for substantially registerless processing A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an arithmetic logic unit, an address multiplexer, and a storage multiplexer. The processor utilizes a data stream... | 04/03/2007 |
| 7197627 | Multiple processor arrangement for conserving power A processing arrangement for a computer comprising: first processor means (1) for processing a first set of instructions; and second processor means (2) for processing a second set of instructions, the second set of instructions being a subset of the first set of in... | 03/27/2007 |
| 7168853 | Digital measuring system and method for integrated circuit chip operating parameters This invention relates to digitally measuring operating parameters, for example, temperature, within a semiconductor chip and making those measurements internally available to hardware, firmware, and software. ... | 01/30/2007 |
| 7103701 | Memory bus interface An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the host device via the host bus, where the address has a first width. Next... | 09/05/2006 |
| 7039739 | Method and apparatus for providing seamless hooking and intercepting of selected kernel and HAL exported entry points In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the in... | 05/02/2006 |
| 7010612 | Universal serializer/deserializer A universal serializer/deserializer (“ser/des”) is disclosed that provides hardware implemented modules of those functions determined to be most applicable to a communications protocol. Functionality that is determined to be more unique for a given protocol is i... | 03/07/2006 |
| 6996747 | Program counter trace stack, access port, and serial scan path A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations. ... | 02/07/2006 |
| 6772326 | Interruptible an re-entrant cache clean range instruction A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An interruptible clean instruction (802) can be executed in a sequenc... | 08/03/2004 |
| 6751788 | Method of testing computer software A method of testing the ability of software modules, each executing particular functions, in a device to cooperate using machine code sequences contained in executing software modules, checks the mutual independence and compatibility of the various technical functio... | 06/15/2004 |
| 6748507 | Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connect... | 06/08/2004 |
| 6678766 | Synchronous communication bus and process for synchronous communication between circuit modules A synchronous communication bus for transferring data between circuit modules (2), which are connected to the communication bus, having at least one data bus (1, 3), a control bus (4) and a bus control unit (5), whereby the circuit modules send an interru... | 01/13/2004 |
| 6646645 | System and method for synchronization of video display outputs from multiple PC graphics subsystems A system and method for synchronization of video raster display outputs from multiple PC graphics subsystems to facilitate synchronized output onto multiple displays are disclosed. The system and method allow multiple graphics subsystems, in a single or m... | 11/11/2003 |
| 6643720 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a re... | 11/04/2003 |
| 6598099 | Data transfer control method, and peripheral circuit, data processor and data processing system for the method A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a re... | 07/22/2003 |
| 6578136 | Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least one recording surface, a decoder circuit which receives code... | 06/10/2003 |
| 6412062 | Injection control mechanism for external events The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match betw... | 06/25/2002 |
| 6397322 | Integrated intrinsically safe input-output module A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device on the hazardous side. The integrated module is configurabl... | 05/28/2002 |
| 6389526 | Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I... | 05/14/2002 |
| 6370606 | System and method for simulating hardware interrupts in a multiprocessor computer system A technique for providing hardware interrupt simulation using the interprocessor interrupt mechanism of the local Advanced Programmable Interrupt Controller (APIC) on a Symmetric Multiprocessor (SMP) System running Windows NT is disclosed. The interrupt s... | 04/09/2002 |
| 6347378 | Techniques and circuits for high yield improvements in programmable devices using redundant logic A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good ... | 02/12/2002 |
| 6272618 | System and method for handling interrupts in a multi-processor computer A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each processor to get currently executing opcode to determine what ... | 08/07/2001 |
| 6243786 | Apparatus and method for generating an interrupt prohibited zone in pipelined data processors In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the microinstructions translated from a macroinstruction using... | 06/05/2001 |
| 6226753 | Single chip integrated circuit with external bus interface A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit outputs the same value as that of the internal signal from each ... | 05/01/2001 |
| 6223274 | Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable between the two processors. The customized processor normally... | 04/24/2001 |
| 6223265 | Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller ... | 04/24/2001 |
| 6205556 | Semiconductor integrated circuit device comprising a memory array and a processing circuit Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network proces... | 03/20/2001 |
| 6175914 | Processor including a combined parallel debug and trace port and a serial port A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the p... | 01/16/2001 |
| 6175890 | Device for efficiently handling interrupt request processes When an interrupt request signal is input, a microprocessor checks, upon termination of an instruction cycle being executed, whether the interrupt request is masked. If the interrupt request is not masked, the microprocessor saves the content of the progr... | 01/16/2001 |
| 6088743 | Processor receiving response request corresponding to access clock signal with buffer for external transfer synchronous to response request and internal transfer synchronous to operational clock A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a re... | 07/11/2000 |
