Did You Know...
...that the Band-Aid Bandage was invented by a Johnson & Johnson employee whose wife had cut herself? Earl Dickson's wife was rather accident prone, so he set out to develop a bandage that she could apply without help. He placed a small piece of gauze in the center of a small piece of surgical tape, and what we know today as the Band Aid bandage was born!
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| Number | Title | Issue Date |
| 7421384 | Semiconductor integrated circuit device and microcomputer development supporting device During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits i... | 09/02/2008 |
| 7409531 | Integrated micro-controller and programmable device A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a micro-controller, a complex programmable logic device, an EEPROM, an SRAM, an... | 08/05/2008 |
| 7356708 | Decryption semiconductor circuit A semiconductor integrated circuit having a plurality of selectable pathways inter-connected to data sources and data destinations; a cryptographic circuit connected to the selectable pathways to selectively receive data from at least one of the data sources, to dec... | 04/08/2008 |
| 7353345 | External observation and control of data in a computing processor A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a d... | 04/01/2008 |
| 7333520 | Apparatus for multiplexing signals through I/O pins One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signa... | 02/19/2008 |
| 7324401 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 01/29/2008 |
| 7277039 | Semiconductor integrated circuit with A/D converter having a ladder-type resistor A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first op... | 10/02/2007 |
| 7272670 | Integrated multimedia system An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia p... | 09/18/2007 |
| 7266667 | Memory access using multiple sets of address/data lines Methods and apparatus for accessing multiple memory arrays within a memory device using multiple sets of address/data lines are provided. The memory arrays may be accessed independently, using separate addresses, in one mode of operation, and accessed using a common... | 09/04/2007 |
| 7263627 | System and method having strapping with override functions A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be te... | 08/28/2007 |
| 7224690 | Method and apparatus for managing transmission and reception of data over a network In a network which includes at least a transmission-side apparatus having a plurality of logical plugs and a reception-side apparatus having a plurality of logical plugs, correspondence between transmission-side logical plugs (e.g., P2 to P4) and recep... | 05/29/2007 |
| 7218562 | Recovering bit lines in a memory array after stopped clock operation In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to the first and second bit lines; and a control circuit coupled to the... | 05/15/2007 |
| 7213117 | 1-chip microcomputer having controlled access to a memory and IC card using the 1-chip microcomputer A 1-chip microcomputer of the present invention has (a) a monitor flag for setting a flag indicating that a specified address space is accessed, (b) an access permission address range setting register, for setting an address range in which an access is permitted whi... | 05/01/2007 |
| 7209140 | System, method and article of manufacture for a programmable vertex processing model with instruction set A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The ope... | 04/24/2007 |
| 7194600 | Method and apparatus for processing data with a programmable gate array using fixed and programmable processors A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues wh... | 03/20/2007 |
| 7185128 | System and method for machine specific register addressing in external devices There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus device... | 02/27/2007 |
| 7185122 | Device and method for controlling data transfer A data transfer control device and method is devoted to control data transfer (i.e., DMA transfer) between a main memory whose storage capacity is arbitrarily set and a buffer memory (e.g., a FIFO memory) incorporated in a peripheral module, wherein a first register... | 02/27/2007 |
| 7180437 | Parallel-to-serial converter Method and system on an aircraft for converting plural data inputs and plural data outputs from a parallel format to a serial format is provided. The system includes an integrated software module that accepts plural variable number of inputs and generates a plural v... | 02/20/2007 |
| 7174415 | Specialized memory device A specialized memory chip which includes an embedded application specific signal processing unit ASSPU. The ASSPU handles one or more predetermined tasks instead of a main processing unit. The ASSPU and the main processing unit can access memory on the memory chip s... | 02/06/2007 |
| 7170513 | System and method for display list occlusion branching A system and method are provided for conditional branching in a hardware graphics pipeline. Initially, a plurality of graphics commands is received. Condition data is then affected based on at least some of the graphics commands utilizing the hardware graphics pipel... | 01/30/2007 |
| 7171542 | Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable inter... | 01/30/2007 |
| 7162716 | Software emulator for optimizing application-programmable vertex processing A central processing unit (CPU) including an operating system for executing code segments capable of performing graphics processing on the CPU. Associated therewith is a graphics application specific integrated circuit (ASIC) for performing graphics processing in ac... | 01/09/2007 |
| 7155597 | Data processing device with aliased data pointer register A data processing device has load and store instructions which address memory with the content of a data pointer register. In a normal mode, the same data pointer register is used for all load and store instructions. In this mode the processor is compatible with a o... | 12/26/2006 |
| 7151709 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 12/19/2006 |
| 7148503 | Semiconductor device, function setting method thereof, and evaluation method thereof The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs... | 12/12/2006 |
| 7139905 | Dynamic endian switching The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may receive a signal from the processor that determines what the endian-ness s... | 11/21/2006 |
| 7107405 | Writing cached data to system management memory In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evict... | 09/12/2006 |
| 7095414 | Blending system and method in an integrated computer graphics pipeline A system and method are provided for a hardware implementation of a blending technique during graphics processing in a graphics pipeline. During processing in the pipeline, a plurality of matrices and a plurality of weight values are received. Also received is verte... | 08/22/2006 |
| 7015838 | Programmable serializing data path A programmable serial data path includes a programmable timing circuit and a parallel to serial module. The programmable timing circuit is operably coupled to generate a first plurality of timing signals when width of parallel input data is of a first multiple and t... | 03/21/2006 |
| 7009607 | Method, apparatus and article of manufacture for a transform module in a graphics processor A method, apparatus and article of manufacture are provided for a transform system for graphics processing as a computer system or on a single integrated circuit. Included is an input buffer adapted for being coupled to a vertex attribute buffer for receiving vertex... | 03/07/2006 |
| 7006101 | Graphics API with branching capabilities A system, method and computer program product are provided for branching during programmable processing utilizing a graphics application program interface in conjunction with a hardware graphics pipeline. Initially, a first instruction defined by the graphics applic... | 02/28/2006 |
| 7003660 | Pipeline configuration unit protocols and communication An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processin... | 02/21/2006 |
| 7002588 | System, method and computer program product for branching during programmable vertex processing A system, method and computer program product are provided for branching during graphics processing. Initially, a first operation is performed on data. In response to the first operation, a branching operation is performed to a second operation. The first operation ... | 02/21/2006 |
| 6996709 | Method for configuring a configurable hardware block by configuring configurable connections provided around a given type of subunit A method for configuring a configurable hardware block includes implementing commands and/or command sequences of a program to be executed. The implementing step includes ascertaining a given type of subunit of a configurable hardware block, the given type of subuni... | 02/07/2006 |
| 6996470 | Systems and methods for geophysical imaging using amorphous computational processing Various systems and methods of the present invention provide amorphous computing systems and methods for use thereof. In some cases, the amorphous computing systems include one or more amorphous hardware elements that are programmed under control of a computer proce... | 02/07/2006 |
| 6992667 | Single semiconductor graphics platform system and method with skinning, swizzling and masking capabilities A graphics hardware system and method are provided for graphics processing. Such system includes a transform module positioned on a single semiconductor platform for transforming graphics data. Coupled to the transform module is a lighting module which is positioned... | 01/31/2006 |
| 6973405 | Programmable interactive verification agent A verification agent can be used to verify hard and/or soft modules under test in an integrated circuit. The integrated circuit contains a processor and memory for storing code executable by the processor. The module under test performs predetermined operations. The... | 12/06/2005 |
| 6954865 | Reduced verification complexity and power saving features in a pipelined integrated circuit An integrated circuit that uses a functional unit that outputs one set of values when in a power saving mode is provided. The functional unit, generally pipelined, is capable of being in the power saving mode dependent on an instruction decode/issue unit, and when i... | 10/11/2005 |
| 6925554 | Method of programming USB microcontrollers An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode. ... | 08/02/2005 |
| 6842818 | Electronic device with card interface When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedu... | 01/11/2005 |
