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| Number | Title | Issue Date |
| 7953958 | Architecture for joint detection hardware accelerator A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and outp... | 05/31/2011 |
| 7805591 | Method and system for dual-core processing This invention describes a baseband dual-core signal processing in mobile communication systems operating according to GSM, GPRS, or EDGE comprising a first digital signal processor adapted to perform tasks on a first time basis and a second digital signal processor... | 09/28/2010 |
| 7685405 | Programmable architecture for digital communication systems that support vector processing and the associated methodology The invention includes an apparatus and the associated method to digitally process data communicated through a communication channel between a transceiver pair. A global control element and programmable algorithm control elements are used to implement an algorithm u... | 03/23/2010 |
| RE40942 | Integrated digital signal processor/general purpose CPU with shared internal memory An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data from a digital signal utilizing a sequence of DSP operations selected b... | 10/20/2009 |
| 7437540 | Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a compl... | 10/14/2008 |
| 7437719 | Combinational approach for developing building blocks of DSP compiler An approach that uses a combinatorial approach by adopting natural language processing with the application of Finite State Morphology (FSM) to transform source code into an efficient assembly code. In one example embodiment, this is accomplished by modifying a sour... | 10/14/2008 |
| 7426500 | Parallel computer architecture of a cellular type, modifiable and expandable This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an invariable binary place fed into central hexagram's CPU controlled by a s... | 09/16/2008 |
| 7421384 | Semiconductor integrated circuit device and microcomputer development supporting device During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in the chip to execute them, and accesses RAM and peripheral circuits i... | 09/02/2008 |
| 7409528 | Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third memory devices, which are connected with the first communication port... | 08/05/2008 |
| 7401205 | High performance RISC instruction set digital signal processor having circular buffer and looping controls A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions... | 07/15/2008 |
| 7389404 | Apparatus and method for matrix data processing A matrix data processor is implemented wherein data elements are stored in physical registers and mapped to logical registers. After being stored in the logical registers, the data elements are then treated as matrix elements. By using a series of variable matrix pa... | 06/17/2008 |
| 7376812 | Vector co-processor for configurable and extensible processor architecture A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/20/2008 |
| 7370150 | System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached... | 05/06/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7356671 | SoC architecture for voice and video over data network applications A system-on-chip (SoC) for voice and video over data network applications includes a first and a second general purpose processors and a plurality of coprocessors. The coprocessors include: a VCODEC engine for video compression/decompression, a security engine for d... | 04/08/2008 |
| 7356633 | Composing on-chip interconnects with configurable interfaces Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output wi... | 04/08/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7340357 | Arbitrary waveform generator with configurable digital signal processing unit An arbitrary waveform generator including a digital signal procession unit and a memory. The digital signal processing unit may be configurable to interconnect a plurality of processing components in different configurations to process data received from the memory ... | 03/04/2008 |
| 7340553 | Data processing device and method for transferring data The data processing device according to the invention comprises a first processing unit (1) linked to a first bus (5), a second processing unit (2) linked to a second bus (6), a first bus master (3) linked to the first bus (5 | 03/04/2008 |
| 7339837 | Configurable embedded processor A configurable processor architecture uses a common simulation database for multiple processor configurations to reduce the cost of producing customized processor configurations. An unchanging core portion is used in each processor configuration. To support differen... | 03/04/2008 |
| 7337110 | Structured VSELP codebook for low complexity search A codebook excited linear prediction coding system providing improved digital speech coding for high quality speech at low bit rates with side-by-side codebooks for segments of the modeled input signal to reduce the complexity of the codebook search. A linear predic... | 02/26/2008 |
| 7337302 | Data processing device A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective da... | 02/26/2008 |
| 7329811 | Musical sound generation device capable of effectively utilizing the access timing for an unused slave sound source A musical tone generating apparatus, which is capable of effectively utilizing the access timing for an unused slave sound source, is provided. The musical tone generating apparatus is composed of a master sound source 1000, which comprises a mode swit... | 02/12/2008 |
| 7330864 | System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for conver... | 02/12/2008 |
| 7328334 | Hardware initialization with or without processor intervention In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may includ... | 02/05/2008 |
| 7325122 | Facilitating inter-DSP data communications A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core couple... | 01/29/2008 |
| 7321559 | System and method of noise reduction in receiving wireless transmission of packetized audio signals A receiver for receiving wireless packetized audio signals having packet headers, and packet payloads including encoded audio signals is provided. The receiver includes an audio decoder for decoding the encoded audio signals into digital audio signals, an audio erro... | 01/22/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7315803 | Verification environment creation infrastructure for bus-based systems and modules A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for... | 01/01/2008 |
| 7312716 | Wireless communication using an intrinsically safe design for use in a hazardous area A wireless circuit setup is used in a hazardous area where the circuit is intrinsically safe and does not require explosion proof containment. In this setup, an intrinsically safe master barrier (420) is used without the use of a resistor and one or more resi... | 12/25/2007 |
| 7313709 | Instruction set with thermal opcode for high-performance microprocessor, microprocessor, and method therefor A method (and system) of managing heat in an electrical circuit, includes using a thermal instruction appended to an instruction to be processed to determine a heat load associated with the instruction. ... | 12/25/2007 |
| 7308488 | Method, system and program products for distributing portal content processing The present invention generally relates to a method, system and program product for distributing portal content processing. Specifically, a request for portal content is received on a surrogate system and then passed to a portal system. The portal system will obtain... | 12/11/2007 |
| 7305676 | Communication device configured for real time processing of user data to be transmitted A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned ... | 12/04/2007 |
| 7304942 | Methods and apparatus for maintaining statistic counters and updating a secondary counter storage via a queue for reducing or eliminating overflow of the counters Methods and apparatus are disclosed for maintaining statistic counters and updating a secondary counter memory via a queue for reducing or eliminating overflow of the counters. Multiple counter values are stored in a primary counter storage. An indication of a parti... | 12/04/2007 |
| 7302532 | Central processing unit A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section disposed in the chip and adapted to couple dat... | 11/27/2007 |
| 7299340 | Data processing device having selective data cache architecture and computer system including the same The disclosure is a data processing device with selective data cache architecture and a computer system including the data processing device. The data processing device is comprised of a microprocessor, a coprocessor, a microprocessor data cache, an X-data cache, an... | 11/20/2007 |
| 7296022 | Method and system for accessing a network database as a web service A method and system for accessing network directory data as uses a Web service as an interface between a directory database and network clients. To support extensibility of the object types in the directory database, directory access methods are defined for a generi... | 11/13/2007 |
| 7292847 | Method for coordinating tasks in a GSM network In a mobile unit of a GSM network (Global System for Mobile Communications), various tasks are performed under real-time constraints. After starting an execution of a first task, the execution of the first task is suspended a plurality of times for a respective plur... | 11/06/2007 |
| 7293159 | Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction se... | 11/06/2007 |
| 7286438 | Dual port memory cell with reduced coupling capacitance and small cell size A dual or multi port memory device including a first group of bit lines associated with the first port a second group of bit lines associated with the second port, wherein the bit lines are arranged in different metalization layers and separated horizontally to redu... | 10/23/2007 |
