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| Number | Title | Issue Date |
| 8190858 | Interface device for interfacing a main processor to processing engines and classifier engines, and methods for configuring and operating interface devices There is disclosed an interface device for interfacing between a main processor and one or more processing engines. The interface device is configurable, so that it may be used with a wide range of processing engines without being redesigned. ... | 05/29/2012 |
| 8145882 | Apparatus and method for processing template based user defined instructions A system implemented in hardware includes a main processing core decoding instructions for out of order execution. The instructions include template based user defined instructions. A user execution block executes the template based user defined instructions. An int... | 03/27/2012 |
| 8127113 | Generating hardware accelerators and processor offloads System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automaticall... | 02/28/2012 |
| 8122229 | Dispatch mechanism for dispatching instructions from a host processor to a co-processor A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and s... | 02/21/2012 |
| 8078838 | Multiprocessor system having multiport semiconductor memory with processor wake-up function responsive to stored messages in an internal register A multiport semiconductor memory device having a processor wake-up function and multiprocessor system, the multiprocessor system including a first processor configured to perform a first predetermined task; a second processor configured to perform a second predeterm... | 12/13/2011 |
| 8055882 | Multiplexing commands from processors to tightly coupled coprocessor upon state based arbitration for coprocessor resources Disclosed is a multiprocessor apparatus including a plurality of processors connected to a common bus, a co-processor provided in common to the processors, an arbitration circuit that arbitrates contention among the processors with respect to use of a resource in th... | 11/08/2011 |
| 8046565 | Accelerator load balancing with dynamic frequency and voltage reduction Systems and methods for accelerators which may execute a program in conjunction with a PC are disclosed. In one embodiment, an accelerator includes a plurality of calculation units, each calculation unit operable to execute the program in parallel, an operation cont... | 10/25/2011 |
| 8032734 | Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor A coprocessor interface unit for interfacing a coprocessor to an out-of-order execution pipeline, and applications thereof. In an embodiment, the coprocessor interface unit includes an in-order instruction queue, a coprocessor load data queue, and a coprocessor stor... | 10/04/2011 |
| 8006069 | Inter-processor communication method Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to relinquish control over at least one of the microprocessor's internal registers. The microprocessor may then ... | 08/23/2011 |
| 8006068 | Processor access to data cache with fixed or low variable latency via instructions to an auxiliary processing unit Access to data storage is described. A general-purpose processor and an auxiliary processing unit (APU) interface coupled to the general-purpose processor are provided. Data storage coupled to the general-purpose processor via the APU interface is provided for a fix... | 08/23/2011 |
| 7987341 | Computing machine using software objects for transferring data that includes no destination information A computing machine includes a first buffer and a processor coupled to the buffer. The processor executes an application, a first data-transfer object, and a second data-transfer object, publishes data under the control of the application, loads the published data i... | 07/26/2011 |
| 7971030 | Method for using multiple processing resources which share multiple co-processor resources An apparatus, method, and system for synchronicity independent, resource delegating, power and instruction optimizing processor is provided where instructions are delegated between various processing resources of the processor. An Integer Processing Unit (IPU) of th... | 06/28/2011 |
| 7962721 | Method and apparatus for management of bus transactions relating to shared resources There is provided an information processing apparatus. The apparatus comprises: a processor; at least one I2C device; and a processor support chip. The processor support chip comprises a local service controller and a jointly addressable memory space and has an inte... | 06/14/2011 |
| 7930519 | Processor with coprocessor interfacing functional unit for forwarding result from coprocessor to retirement unit A processor unit and a coprocessor unit are disclosed. In one embodiment, the processor unit includes a functional unit that receives a set of instructions in an instruction stream and provides the set of instructions to the coprocessor unit. The coprocessor execute... | 04/19/2011 |
| 7925862 | Coprocessor forwarding load and store instructions with displacement to main processor for cache coherent execution when program counter value falls within predetermined ranges A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and... | 04/12/2011 |
| 7925863 | Hardware device comprising multiple accelerators for performing multiple independent hardware acceleration operations Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can b... | 04/12/2011 |
| 7900021 | Image processing apparatus and image processing method An image processing apparatus for storing taken image data into a memory and for reading the stored image data to effect image processing thereof, including: a storage section for storing sequence codes that indicate processing procedures of a series of image proces... | 03/01/2011 |
| 7886129 | Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially ... | 02/08/2011 |
| 7877576 | Processing system having co-processor for storing data When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction “GETACX Dm,Dn” performs saving of necessary data from all registers. “Dm” is a value output from a g... | 01/25/2011 |
| 7865697 | Apparatus for and method of processor to processor communication for coprocessor functionality activation A mechanism enabling a processor in a multiprocessor complex to function as a coprocessor to execute a specific function. The method includes a mechanism for activating a coprocessor to function as a coprocessor as well as a mechanism to execute a coprocessor reques... | 01/04/2011 |
| 7856545 | FPGA co-processor for accelerated computation A co-processor module for accelerating computational performance includes a Field Programmable Gate Array (“FPGA”) and a Programmable Logic Device (“PLD”) coupled to the FPGA and configured to control start-up configuration of the FPGA. A non-volatile memory... | 12/21/2010 |
| 7840781 | Circuit arrangement for profiling a programmable processor connected via a uni-directional bus Various approaches for profiling a target system are described. In one approach, a uni-directional, point-to-point bus has a single input port and a single output port. A target processor has a trace port coupled to the input port of the bus and is configured to exe... | 11/23/2010 |
| 7831805 | Coupling a general purpose processor to an application specific instruction set processor Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction se... | 11/09/2010 |
| 7822945 | Configuration managing device for a reconfigurable circuit A semiconductor device including a multi-layer interconnection substrate having a signal distribution interconnection and a power supply line and semiconductor circuit blocks installed on the multi-layer interconnection substrate for performing required operations. ... | 10/26/2010 |
| 7805590 | Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence A coprocessor (14) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor (12). It is important to allow efficient communication and interfacing between the processor (12) and... | 09/28/2010 |
| 7802075 | Synchronized high-assurance circuits A high-assurance system for processing information is disclosed. The high-assurance system comprising first and second processors, a task matching circuit, and first and second outputs. The task matching circuit configured to determine a software routine is ready fo... | 09/21/2010 |
| 7788469 | Information processing device having arrangements to inhibit coprocessor upon encountering data that the coprocessor cannot handle A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transf... | 08/31/2010 |
| 7788470 | Shadow pipeline in an auxiliary processor unit controller A method and controller for supporting out of order execution of instructions is described. A microprocessor is coupled to a coprocessor via a controller. Instructions are received by the microprocessor and the controller. Indices respectively associated with the in... | 08/31/2010 |
| 7769982 | Data processing apparatus and method for accelerating execution of subgraphs A data processing apparatus and method are provided for processing data under control of a program having program instructions including sequences of individual program instructions corresponding to computational subgraphs identified within the program. Each computa... | 08/03/2010 |
| 7765383 | Data processing unit and data processing apparatus using data processing unit A storage unit retains processing target data, a data processing circuit processes the data retained in the storage unit, a connection unit is connected to a processing device that executes a computer program, and a control unit invalidates, when a predetermined con... | 07/27/2010 |
| 7721069 | Low power, high performance, heterogeneous, scalable processor architecture One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in... | 05/18/2010 |
| 7711925 | Information-processing device with transaction processor for executing subset of instruction set where if transaction processor cannot efficiently execute the instruction it is sent to general-purpose processor via interrupt An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the... | 05/04/2010 |
| 7698533 | Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially ... | 04/13/2010 |
| 7689810 | Processor generating control signals including detection duration for satellite positioning system ranging signal detection circuit A circuit to detect position signals in a mobile station includes a general-purpose processor to generate instructions for execution of at least one signal detection algorithm and to carry out at least one other function not associated with the signal detection algo... | 03/30/2010 |
| 7685404 | Program subgraph identification An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within the program. A... | 03/23/2010 |
| 7669037 | Method and apparatus for communication between a processor and hardware blocks in a programmable logic device Method and apparatus for communication between hardware blocks and a processor in a programmable logic device is described. A shared memory is provided along with a memory controller for controlling access to the shared memory. An interface is configured to receive ... | 02/23/2010 |
| 7664930 | Add-subtract coprocessor instruction execution on complex number components with saturation and conditioned on main processor condition flags Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex d... | 02/16/2010 |
| 7647475 | System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue A processor includes a coprocessor interface unit that couples a coprocessor that executes instructions in-program order to an execution unit that executes instructions out-of-program order. The coprocessor interface unit includes a coprocessor store data queue. If ... | 01/12/2010 |
| 7600096 | Coprocessor extension architecture built using a novel split-instruction transaction model A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction transaction employed to provide operands and instructions to an extens... | 10/06/2009 |
| 7590822 | Tracking an instruction through a processor pipeline Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is coupled between the coprocessor and a processor, where the controller is... | 09/15/2009 |
