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| Number | Title | Issue Date |
| 7917730 | Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller A multi-chip processor apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk that communicates information between multiple compute elements situated along the primar... | 03/29/2011 |
| 7558944 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 07/07/2009 |
| 7412588 | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted pac... | 08/12/2008 |
| 7409251 | Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writ... | 08/05/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7318146 | Peripheral device with hardware linked list A linked list is implemented in hardware. Various registers within the linked list are writeable until a control register is written, rendering the registers read-only. A computer peripheral includes the hardware linked list to provide a list of capabilities to a qu... | 01/08/2008 |
| 7305540 | Method and apparatus for data processing Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled ... | 12/04/2007 |
| 7296096 | Method and system for configuring an interconnect device In one embodiment, a system for configuring an interconnect device includes a non-volatile storage device to store configuration data associated with the interconnect device and a configuration interface to request the configuration data from the non-volatile storag... | 11/13/2007 |
| 7283418 | Memory device and method having multiple address, data and command buses A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by ... | 10/16/2007 |
| 7281667 | Method and structure for implementing secure multichip modules for encryption applications A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conduc... | 10/16/2007 |
| 7281063 | Signal routing circuit board coupling controller and storage array circuit board for storage system A signal routing circuit board has electronics common to circuit boards coupled to the signal routing circuit board. The signal routing circuit board may be coupled to a storage array circuit board and at least one input/output (I/O) controller circuit board. The st... | 10/09/2007 |
| 7269719 | Predicated execution using operand predicates Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will ... | 09/11/2007 |
| 7254727 | Information processor with suppressed cache coherence in low power mode An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the powe... | 08/07/2007 |
| 7251720 | Flexible digital signal processor The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system. The digital signal processor is a flexible digital signal processor and comprises... | 07/31/2007 |
| 7249239 | Using run-time generated instructions in processors supporting wider immediate addressing than register addressing The processor typically uses address registers having a particular bit width to access lines within an address space. The bit width limits the address space to a particular size. Techniques are provided for expanding the allowed address bit width and the correspondi... | 07/24/2007 |
| 7243181 | Signal bus arrangement In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal lines of the same buses transmit signals changed substantially at the... | 07/10/2007 |
| 7233534 | Electronic circuit package An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having... | 06/19/2007 |
| 7231464 | Management system for multimodule multiprocessor machines The present invention relates to a global management system for a multimodule, multiprocessor machine (PK). The system is characterized in that it comprises an independent module (SM) dedicated to the global management of a plurality of first modules (M1 thro... | 06/12/2007 |
| 7225349 | Power supply voltage droop compensated clock modulation for microprocessors A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected. ... | 05/29/2007 |
| 7216213 | Method of analyzing data utilizing queue entry A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queui... | 05/08/2007 |
| 7206894 | Microcomputer application system, microcomputer, signal processing system and signal processing LSI An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM1 stored in the external ROM to a high-speed processing region of an internal RAM. When a fetch address AZ1... | 04/17/2007 |
| 7207014 | Method for modular design of a computer system-on-a-chip In a computer system having a device and a communications link for communicating with the device. A method for dynamically managing power consumption by the computer system comprises associating a particular device identifier with the device. Communications are moni... | 04/17/2007 |
| 7206875 | Expander device capable of persistent reservations and persistent affiliations A method according to one embodiment may include creating at least one of a persistent reservation and a persistent affiliation between one or more target SATA storage devices and one or more initiator engines. Of course, many alternatives, variations, and modificat... | 04/17/2007 |
| 7200735 | High-performance hybrid processor with configurable execution units A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in reconfigurable logic. New instructions set configurations can be discovered and... | 04/03/2007 |
| 7142443 | Reduced data line pre-fetch scheme A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefet... | 11/28/2006 |
| 7137095 | Freeway routing system for a gate array A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field pro... | 11/14/2006 |
| 7136944 | Method and apparatus for using address traps to pace writes to peripheral devices A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure. ... | 11/14/2006 |
| 7133954 | Data bus system for micro controller Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system includes an external access bus used when data is output from the CPU... | 11/07/2006 |
| 7130934 | Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind... | 10/31/2006 |
| 7120069 | Electronic circuit package An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having... | 10/10/2006 |
| 7117342 | Implicitly derived register specifiers in a processor A processor executes an instruction set including instructions in which a register specifier is implicitly derived, based on another register specifier. One technique for implicitly deriving a register specifier is to add or subtract one from a specifically-defined ... | 10/03/2006 |
| 7110830 | Microprocessor system and method for protecting the system from the exchange of modules A microprocessor system includes a plurality of modules, among them a microprocessor and at least one storage module for storing the code and/or data for the microprocessor. Stored, in a non-changeable manner, in at least one of the modules, referred to as exchange-... | 09/19/2006 |
| 7111155 | Digital signal processor computation core with input operand selection from operand bus for dual operations A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features... | 09/19/2006 |
| 7103753 | Backplane system having high-density electrical connectors A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by replacing the printed circuit board incorporating the processor. Simil... | 09/05/2006 |
| 7103523 | Method and apparatus for implementing multiple configurations of multiple IO subsystems in a single simulation model A method and apparatus are provided for implementing multiple configurations of multiple input/output (IO) subsystems in a single simulation model. At least one bus routing switch is included in the single simulation model. Each bus routing switch includes a plurali... | 09/05/2006 |
| 7101770 | Capacitive techniques to reduce noise in high speed interconnections Improved methods and structures are provided using capacitive techniques to reduce noise in high speed interconnections, such as in CMOS integrated circuits. The present invention offers an improved signal to noise ration. The present invention provides for the fabr... | 09/05/2006 |
| 7096303 | Method and apparatus for configuring an integrated bus A configurable bus interface circuit includes an internal bus bridge and an internal circuit. The configurable bus interface circuit also includes an internal I/O circuit couplable to an external circuit, via the internal bus bridge. The configurable bus interface c... | 08/22/2006 |
| 7076686 | Hot swapping memory method and system A method of hot swapping memory is described. A memory system includes a plurality of memory banks such that a memory word is divided into the memory banks. The memory system is provided a spare memory bank. One of the memory banks is selected to be replaced. The me... | 07/11/2006 |
| 7054984 | Structure and method for extended bus and bridge in the extended bus A structure and a method for an extended bus and a bridge in the extended bus are disclosed. The structure of the extended bus has a first accelerated graphics port bus, a first bridge, a second accelerated graphics port bus and a first extended bus. The first bridg... | 05/30/2006 |
