Bizarre Patents
Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 8190867 | Packing two packed signed data in registers with saturation A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers, and to specify a second source register having a second packed signed 16-bit integers. A functional unit t... | 05/29/2012 |
| 7991987 | Comparing text strings A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled ... | 08/02/2011 |
| 7966482 | Interleaving saturated lower half of data elements from two source registers of packed data An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data responsive to a pack instruction received by the decoder. A first packed... | 06/21/2011 |
| 7895423 | Method for extracting fields from packets having fields spread over more than one register Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction ex... | 02/22/2011 |
| 7840789 | Data hiding in compiled program binaries for supplementing computer functionality Bit reductions in program instructions are achieved by determining the set of bit patterns in bit locations of the instructions. If only a subset of bit patterns is present in the instructions, they may be represented by an index value having a smaller number of bit... | 11/23/2010 |
| 7822955 | Data processing apparatus and method for utilizing endianess independent data values The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be performed on particular sections of an input data word. The data process... | 10/26/2010 |
| 7814303 | Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed by the vector-based execution unit. A swizzle sequence instruction i... | 10/12/2010 |
| 7730292 | Parallel subword instructions for directing results to selected subword locations of data processor result register In the context of a microprocessor and a program, the invention provides parallel subword compare instructions that store results in a selectable intra-register subword location. In a targeting approach, an instruction permits the location to be specified; alternati... | 06/01/2010 |
| 7725699 | Data byte insertion circuitry A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data words before and after data byte insertion points of the current and ... | 05/25/2010 |
| 7721077 | Performing endian conversion A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB) instruction. An endian conversion is performed on the data that is moved into an... | 05/18/2010 |
| 7711938 | Multistandard video decoder and decompression system for processing encoded bit streams including start code detection and methods relating thereto A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit strea... | 05/04/2010 |
| 7698542 | Circuit and method for comparing program counter values A circuit and a method of examining in a microprocessor a section of a first range of values and a second range of values each comprising a lower boundary value and an upper boundary value is disclosed. The method includes examining whether a value of the first rang... | 04/13/2010 |
| 7600104 | Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length System and method are provided for parallel vector data processing having a data processor capable of vector data having a defined first bit-length. In one embodiment, at least one of first and second operand registers is used for storing operands, and an additional... | 10/06/2009 |
| 7590832 | Information processing device, compressed program producing method, and information processing system An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the output from the instruction buffer; an instruction decompression section... | 09/15/2009 |
| 7581091 | System and method for extracting fields from packets having fields spread over more than one register Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction ex... | 08/25/2009 |
| 7565516 | Word reordering upon bus size resizing to reduce Hamming distance In a system having a first device 10 and a second device 8 between which data values are transferred via an N-bit bus, a resizing unit 18 and an M-bit bus, reordering of the data is performed such that portions of the original N-bit data words h... | 07/21/2009 |
| 7529918 | System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a plurality of predicate registers, and at least one execution unit con... | 05/05/2009 |
| 7500089 | SIMD processor with exchange sort instruction operating or plural data elements simultaneously An SIMD type microprocessor having a plurality of processor elements, wherein data stored in a specific register included in each processor element and data stored in an operand-designated source register are compared based on a first type of instruction; after the ... | 03/03/2009 |
| 7493481 | Direct hardware processing of internal data structure fields In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a ... | 02/17/2009 |
| 7464254 | Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of... | 12/09/2008 |
| 7464255 | Using a shuffle unit to implement shift operations in a processor A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The shuffle unit is adapted to support shift operations as well. In response... | 12/09/2008 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7441104 | Parallel subword instructions with distributed results The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the para... | 10/21/2008 |
| 7434040 | Copying of unaligned data in a pipelined operation Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16 bytes of data from an unaligned data area to an aligned data area during... | 10/07/2008 |
| 7424600 | Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency The information processing apparatus includes: a process unit having one or more registers that retain data used for calculation; a compression unit that compresses and saves the content in the register to a stack memory; and a decompression unit that decompresses a... | 09/09/2008 |
| 7403835 | Device and method for programming an industrial robot In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image surface as movement and/or processing operations by the robot on the bas... | 07/22/2008 |
| 7389408 | Microarchitecture for compact storage of embedded constants An instruction stream having variable length instructions with embedded constants (e.g. immediate values and displacements) is translated into a stream of operations and a corresponding stream of bit fields, enabling advantageous compact storage of the embedded cons... | 06/17/2008 |
| 7386699 | Aligning IP payloads on memory boundaries for improved performance at a switch A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module prefixes non-data bits to... | 06/10/2008 |
| 7370184 | Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post pro... | 05/06/2008 |
| 7370167 | Time slicing device for shared resources and method for operating the same Broadly speaking, a device for addressing a shared resource is disclosed. The device includes at least one register in communication with the shared resource. The at least one register is configured to hold an address that is to be provided to the shared resource up... | 05/06/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7356455 | Optimized interface for simulation and visualization data transfer between an emulation system and a simulator An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buff... | 04/08/2008 |
| 7356676 | Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a copr... | 04/08/2008 |
| 7356083 | Data compression system and method This invention produces data packets that can vary in length and/or data compression ratio. First, an algorithm is employed to transform a data signal into fixed or variable length data packets at variable data compression ratios. If the algorithm produces fixed len... | 04/08/2008 |
| 7353371 | Circuit to extract nonadjacent bits from data packets A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. I... | 04/01/2008 |
| 7350058 | Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination va... | 03/25/2008 |
| 7346430 | Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple channels by using the existing systems which are formed on the premise of... | 03/18/2008 |
| 7343389 | Apparatus and method for SIMD modular multiplication An apparatus and method for single instruction multiple data (SIMD) modular multiplication are described. In one embodiment, the method includes selection of modular multiplication method available from an operating environment. Once the multiplication method is sel... | 03/11/2008 |
| 7343471 | Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, eac... | 03/11/2008 |
| 7339573 | Method and system for navigating within an image The present invention relates to at least one image section which is represented according to a zoom factor selected from a number of different zoom factors. Either the represented image section is changed when the zoom factor is lower than a zoom threshold value, o... | 03/04/2008 |
