Did You Know...
...that the Eveready Battery began as an invention called the "electric flowerpot," which was a tube with a battery and light bulb inside? The idea was to fasten this gizmo to the side of a flowerpot so it would illuminate the flowers from the bottom. The idea died on the vine and the businessman who licensed the flower pot, Conrad Huber, was left with a pile of useless tubes -- until he found a way to market them as batteries to light the world!
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| Number | Title | Issue Date |
| 8190854 | System and method of processing data using scalar/vector instructions A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into packets of instructions of different types for parallel execution by a p... | 05/29/2012 |
| 8090928 | Methods and apparatus for processing scalar and vector instructions In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines coupled to the scalar computation unit, where the engines are adapted ... | 01/03/2012 |
| 7908460 | Method and apparatus for obtaining a scalar value directly from a vector register A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits... | 03/15/2011 |
| 7895411 | Physics processing unit One embodiment of the invention sets forth a hardware-based physics processing unit (PPU) having unique architecture designed to efficiently generate physics data. The PPU includes a PPU control engine (PCE), a data movement engine and a floating point engine (FPE).... | 02/22/2011 |
| 7739480 | Method and apparatus for obtaining a scalar value directly from a vector register A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits... | 06/15/2010 |
| 7437521 | Multistream processing memory-and barrier-synchronization method and apparatus A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects o... | 10/14/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
| 7337278 | System, method and storage medium for prefetching via memory block tags A system for memory management including a tag cache in communication with one or more cache devices in a storage hierarchy. The tag cache includes tags of recently accessed memory blocks where each tag corresponds to one of the pages and each tag includes tag conte... | 02/26/2008 |
| 7334110 | Decoupled scalar/vector computer architecture system and method In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of the scalar processing unit from that of the vector processing unit, ... | 02/19/2008 |
| 7315849 | Enterprise-wide data-warehouse with integrated data aggregation engine An enterprise-wide data-warehouse comprising a database management system (DBMS) including a relational datastore storing data in tables. An aggregation module, operatively coupled to the relational datastore aggregates the data stored in the tables of the relationa... | 01/01/2008 |
| 7315307 | Methods and systems for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 01/01/2008 |
| 7315308 | Methods and system for merging graphics for display on a computing device Disclosed are methods and systems that allow video applications to merge their outputs for display and to transform the outputs of other applications before display. A graphics arbiter tells applications the estimated time when the next frame will be displayed on a ... | 01/01/2008 |
| 7305540 | Method and apparatus for data processing Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled ... | 12/04/2007 |
| 7281055 | Routing mechanisms in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 10/09/2007 |
| 7254696 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit th... | 08/07/2007 |
| 7251698 | Address space management in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 07/31/2007 |
| 7249224 | Methods and apparatus for providing early responses from a remote data cache According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 07/24/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7213131 | Programmable processor and method for partitioned group element selection operation A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data ... | 05/01/2007 |
| 7197623 | Multiple processor cellular radio Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor comprises a program part (30) including an incrementation registe... | 03/27/2007 |
| 7191264 | Disk control apparatus Disclosed is a disk control apparatus with excellent scalability realized on the same architecture, in high quality and reliability, regardless of its scale. Each of a plurality of channel interface units and a cache memory unit as well as each of a plurality of dis... | 03/13/2007 |
| 7181601 | Method and apparatus for prediction for fork and join instructions in speculative execution A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a spe... | 02/20/2007 |
| 7167972 | Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value ... | 01/23/2007 |
| 7165133 | Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or bur... | 01/16/2007 |
| 7155525 | Transaction management in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 12/26/2006 |
| 7143306 | Data storage system A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for ... | 11/28/2006 |
| 7130985 | Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous reg... | 10/31/2006 |
| 7124280 | Execution control apparatus of data driven information processor for instruction inputs An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one addr... | 10/17/2006 |
| 7111120 | Scalable disk array controller This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such system... | 09/19/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7103636 | Methods and apparatus for speculative probing of a remote cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or ... | 09/05/2006 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 09/05/2006 |
| 7096292 | On-chip inter-subsystem communication A data transfer interface includes facilities for a subsystem including the data transfer interface to internally prioritize transactions with other subsystems, using facilities of the data transfer interface. In one embodiment, the subsystem also includes with the ... | 08/22/2006 |
| 7047393 | Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a targ... | 05/16/2006 |
| 7043607 | Information processing system and cache flash control method used for the same The vector unit 21 outputs a first flash address to the flash address array 24. The vector unit 31 outputs a second flash address to the flash address array 34. In the master unit 2, the flash address array 24 compares an ad... | 05/09/2006 |
| 7032101 | Method and apparatus for prioritized instruction issue queue in a processor An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of instruction queues storing the instruction of differing priorities, and a... | 04/18/2006 |
| 7028143 | Narrow/wide cache A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said fir... | 04/11/2006 |
| 7028145 | Protocol processor intended for the execution of a collection of instructions in a reduced number of operations Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation registe... | 04/11/2006 |
| 7027446 | Method and apparatus for set intersection rule matching A method and apparatus for of high-speed and memory efficient rule matching, the rule matching being performed on an m-dimensional universe with each dimension bound by a given range of coordinate values, and a set of rules that apply to an undetermined number of co... | 04/11/2006 |
| 7024595 | Method for controlling storage system A storage system including: channel control portions each including a circuit board on which a file access processing portion for receiving file-by-file data input/output requests sent from information processors through a network and an I/O processor for outputting... | 04/04/2006 |
