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| Number | Title | Issue Date |
| 7600103 | Speculatively scheduling micro-operations after allocation Apparatus, systems and methods for speculative scheduling of uops after allocation are disclosed including an apparatus having logic to schedule a micro-operation (uop) for execution before source data of the uop is ready. The apparatus further includes logic to can... | 10/06/2009 |
| 7376811 | Method and apparatus for performing computations and operations on data using data steering A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware engine performs operations and computations on data as the data traverses ... | 05/20/2008 |
| 7254689 | Decompression of block-sorted data In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a pr... | 08/07/2007 |
| 7130934 | Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind... | 10/31/2006 |
| 7103758 | Microcontroller performing safe recovery from standby mode A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcont... | 09/05/2006 |
| 6948005 | Peripheral device for programmable controller A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices o... | 09/20/2005 |
| 6850993 | Peripheral device for programmable controller A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices o... | 02/01/2005 |
| 6804759 | Method and apparatus for detecting pipeline address conflict using compare of byte addresses In a computer processor, a low-order portion of a virtual address for a pipelined operation is compared directly with the corresponding low-order portions of addresses of operations below it in the pipeline to detect an address conflict, without first translating th... | 10/12/2004 |
| 6757818 | Programmable microcontroller for controlling multichannel sequences of states to be processed in each processing period A programmable controller for controlling a multi-channel sequential processing of states based on a prescribed state transitions. The microcontroller has a state register for each of the channels for holding the state data to be processed in the channel in the next... | 06/29/2004 |
| 6694426 | Method and apparatus for staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein... | 02/17/2004 |
| 6687810 | Method and apparatus for staggering execution of a single packed data instruction using the same circuit A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein... | 02/03/2004 |
| 6662249 | System and method for conversion of addresses of varying bit lengths between a bus and a device controller A device, method and computer program for communicating between a device controller and an industry standard bus. This device method and computer program requires no modification of the core logic of the device driver even though the data and commands tra... | 12/09/2003 |
| 6650330 | Graphics system and method for processing multiple independent execution threads A method, apparatus and article of manufacture are provided for sequencing graphics processing in a transform or lighting operation. A plurality of mode bits are first received which are indicative of the status of a plurality of modes of process operatio... | 11/18/2003 |
| 6629237 | Solving parallel problems employing hardware multi-threading in a parallel processing environment A computer instruction includes a command instruction to issue a memory reference to an address in a memory shared among threads executing in microprocessors while a context of a thread is inactive.... | 09/30/2003 |
| 6269440 | Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is... | 07/31/2001 |
| 6201488 | CODEC for consecutively performing a plurality of algorithms A CODEC has a DSP which can consecutively execute a plurality of algorithms without restriction of a memory capacity. The DSP performs an encoding/decoding operation on a digital signal. A program memory stores a program divided into a plurality of block ... | 03/13/2001 |
| 6161166 | Instruction cache for multithreaded processor A multithreaded processor includes a level one instruction cache shared by all threads. The I-cache is accessed with an instruction unit generated effective address, the I-cache directory containing real page numbers of the corresponding cache lines. A se... | 12/12/2000 |
| 6105125 | High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers. Information bits about the instruction are added to the tab... | 08/15/2000 |
| 6035394 | System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the i... | 03/07/2000 |
| 6026489 | Signal processor capable of executing microprograms with different step sizes A signal processor stores at least one microprogram having m steps in total smaller in number than n steps which are to be executed within one sampling repetition period. A count corresponding to each of the n steps are generated. M steps of the at least ... | 02/15/2000 |
| 5948096 | Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes A self-timed instruction marking circuit includes a prefix handling system for processing instruction bytes having prefix bytes. Length decoders receive instruction data bytes, and perform length decoding independently of the other length decoders in the ... | 09/07/1999 |
| 5925125 | Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The pre-verification function, contained within CPU execution unit microcode, sets a return value in a progra... | 07/20/1999 |
| 5664138 | Apparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actually occurs A parallel processing control apparatus comprises processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing statuses of the processing blocks; an instruction feeder for simultaneously allo... | 09/02/1997 |
| 5657486 | Automatic test equipment with pipelined sequencer Automatic test equipment utilizing a pipelined sequencer to retrieve test vectors from a random access memory during execution of a test pattern. The order of execution of the test vectors need not be sequential and can be dynamically altered by condition... | 08/12/1997 |
| 5454090 | Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units An apparatus for furnishing instructions having a multi-stage pipeline processing unit for processing at least a "fetch instruction" phase, a "decode instruction" phase and an "execute instruction" phase, includes a memory; an address register having cont... | 09/26/1995 |
| 5454086 | Dynamic program analyzer facility Provides a dynamic execution link between an analyzer program and each hook instruction in a program. Special types of hook instructions are provided for use in a hooked program. The link causes the analyzer program to execute as part of a continuous unin... | 09/26/1995 |
| 5410658 | Microprocessor for carrying out a plurality of different microprograms at the same time and method for controlling the microprocessor The inventive microprocessor includes a first section which runs a microprogram pertinent to a macroinstruction and a second section which runs microprograms that are independent of the macroinstruction, with the first and second sections being operated s... | 04/25/1995 |
| 4890218 | Variable length instruction decoding apparatus having cross coupled first and second microengines A pipeline computer architecture having two interconnected microengines operating simultaneously in an instruction preparation unit of a pipeline computer system. Each microengine operates on the same portion or different portions of an instruction concur... | 12/26/1989 |
| 4841434 | Control sequencer with dual microprogram counters for microdiagnostics A microprogrammed control unit of an information processing system having a control sequencer with dual microprogram counters for performing microdiagnostics simultaneously with performing macroprograms. The microdiagnostics comprise background and operab... | 06/20/1989 |
| 4821187 | Processor capable of executing one or more programs by a plurality of operation units A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second progr... | 04/11/1989 |
| 4499604 | Digital data processing system for executing instructions containing operation codes belonging to a plurality of operation code sets and names corresponding to name table entries A digital computer system having a memory for storing and providing data including instructions and a processor for processing data in response to the instructions and providing memory operation specifiers to the memory which specify an address of a data ... | 02/12/1985 |
| 4439827 | Dual fetch microsequencer A dual fetch microsequencer having two single-ported microprogram memories wherein both the sequential and jump address microinstructions of a binary conditional branch can be simultaneously prefetched, one from each memory. The microprogram is assembled ... | 03/27/1984 |
| 4399505 | External microcode operation in a multi-level microprocessor A data processing system the central processing unit (CPU) of which is responsive to and executes microinstructions generated by the decoding of macroinstructions so as to provide one or more data processing operations. The system is arranged so that such... | 08/16/1983 |
| 4367524 | Microinstruction execution unit for use in a microprocessor An execution unit which is part of a general-purpose microprocessor, partitioned between two integrated circuit chips, with the execution unit on one chip and an instruction unit on another chip. The execution unit provides the interface for accessing a m... | 01/04/1983 |
| 4320453 | Dual sequencer microprocessor A control section consisting of an address processing circuit and two sequencers for use in a programmable microprocessor. The address processing circuit has two sets of input lines and one set of output lines, and is adapted to convert address informatio... | 03/16/1982 |
| 4021779 | Microprogram control units A microprogram control unit comprises a microprogram store and an interactive processor processing the micro instructions issued by the microprogram store to produce expanded system control signals, at least some of the processing elements of the interact... | 05/03/1977 |
