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| Number | Title | Issue Date |
| 8190864 | APIC implementation for a highly-threaded x86 processor Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a... | 05/29/2012 |
| 8190865 | Instruction encoding for system register bit set and clear An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kern... | 05/29/2012 |
| 8190866 | Interrupt handling Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread... | 05/29/2012 |
| 8171270 | Asynchronous control transfer Methods and apparatus to perform asynchronous control transfer are described. In one embodiment, upon occurrence of an event (e.g., an architectural event), a service routine data block (SRDB) is accessed via a service routine base pointer (SRDS) and a service routi... | 05/01/2012 |
| 8151098 | Periodic signal processing apparatus A signal processing apparatus for processing a periodic signal outputted from a signal source has a central processing unit and a task switch timer. The central processing unit performs multiple tasks including a signal processing task in parallel. In the signal pro... | 04/03/2012 |
| 8140834 | System, method and computer program product for providing a programmable quiesce filtering register A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is i... | 03/20/2012 |
| 8127121 | Apparatus for executing programs for a first computer architechture on a computer of a second architechture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 02/28/2012 |
| 8103861 | Method and system for presenting an interrupt request to processors executing in lock step A method and system of presenting an interrupt request to processors executing in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor configured to execute a program, a second processor configured to execute a d... | 01/24/2012 |
| 8090935 | Direct register access for host simulation Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Variou... | 01/03/2012 |
| 8086832 | Structure for dynamically adjusting pipelined data paths for improved power management A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a p... | 12/27/2011 |
| 8082429 | Information processing apparatus and exception control circuit An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from ... | 12/20/2011 |
| 8078853 | Explicit control of speculation Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocess... | 12/13/2011 |
| 8078854 | Using register rename maps to facilitate precise exception semantics One embodiment of the present invention provides a system that facilitates precise exception semantics. The system includes a processor that uses register rename maps to support out-of-order execution, where the register rename maps track mappings between native arc... | 12/13/2011 |
| 8074060 | Out-of-order execution microprocessor that selectively initiates instruction retirement early A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instru... | 12/06/2011 |
| 8051278 | Microcomputer and method of setting operation of microcomputer Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address s... | 11/01/2011 |
| 8019983 | Setting a flag bit to defer event handling to a safe point in an instruction stream Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if... | 09/13/2011 |
| 8001364 | Dynamically migrating channels In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depe... | 08/16/2011 |
| 7996662 | Floating point status/control register encodings for speculative register field In one embodiment, a processor comprises a plurality of storage locations, a decode circuit, and a status/control register (SCR). Each storage location is addressable as a speculative register and is configured to store result data generated during execution of an i... | 08/09/2011 |
| 7996663 | Saving and restoring architectural state for processor cores A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing element, such as a core, is concurrently saved upon being updated. A remaining portion of the architectura... | 08/09/2011 |
| 7984281 | Shared interrupt controller for a multi-threaded processor A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selec... | 07/19/2011 |
| 7979686 | System and method for isochronous task switching via hardware scheduling A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processo... | 07/12/2011 |
| 7966481 | Computer system and method for executing port communications without interrupting the receiving computer A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent proces... | 06/21/2011 |
| 7966480 | Register pointer trap to prevent errors due to an invalid pointer value in a register Trap flags and a pointer trap are associated with registers in a processor. Each trap flag indicates whether a corresponding register has been written with valid data. If not, the trap flag is set to indicate that the register corresponding to the trap flag contains... | 06/21/2011 |
| 7949863 | Inter-port communication in a multi-port memory device A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each po... | 05/24/2011 |
| 7934082 | Information processing apparatus and exception control circuit An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from... | 04/26/2011 |
| 7917740 | Virtualization assist for legacy x86 floating point exception handling In one embodiment, a processor comprises an execution core configured to detect a freeze event responsive to an error indication, an ignore error indication, and an instruction in a guest. The instruction belongs to a predefined subset of instructions associated wit... | 03/29/2011 |
| 7913070 | Time-of-life counter for handling instruction flushes from a queue Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue ... | 03/22/2011 |
| 7890740 | Processor comprising a first and a second mode of operation and method of operating the same A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in... | 02/15/2011 |
| 7886135 | Pipeline replay support for unaligned memory operations Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the executio... | 02/08/2011 |
| 7882339 | Primitives to enhance thread-level speculation A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or mo... | 02/01/2011 |
| 7870372 | Interrupt handling A system, apparatus and method for interrupt handling on a multi-thread processing device are described herein. Embodiments of the present invention provide a multi-thread processing device for interrupt handling including an interrupt block to provide interrupt sig... | 01/11/2011 |
| 7865706 | Information processing method and instruction generating method According to a generated instruction, the present invention provides an information processing method for performing processing by using a CPU that comprises at least one register. The method comprises the steps of: judging whether or not each of the registers is va... | 01/04/2011 |
| 7861072 | Throwing one selected representative exception among aggregated multiple exceptions of same root cause received from concurrent tasks and discarding the rest Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception resu... | 12/28/2010 |
| 7853779 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 12/14/2010 |
| 7840788 | Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a bra... | 11/23/2010 |
| 7836291 | Method, medium, and apparatus with interrupt handling in a reconfigurable array A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for ha... | 11/16/2010 |
| 7831818 | Exception-based timer control A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in respons... | 11/09/2010 |
| 7805596 | Highly integrated multiprocessor system In a multi-processor system (100), when a first processor interrupt generation unit (24) has executed a call command or a jump command in a main routine being executed, it generates an interrupt to a second processor. Upon reception of the interrupt fr... | 09/28/2010 |
| 7774585 | Interrupt and trap handling in an embedded multi-thread processor to avoid priority inversion and maintain real-time operation A real-time, multi-threaded embedded system includes rules for handling traps and interrupts to avoid problems such as priority inversion and re-entrancy. By defining a global interrupt priority value for all active threads and only accepting interrupts having a pri... | 08/10/2010 |
| 7765388 | Interrupt verification support mechanism The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the pro... | 07/27/2010 |
