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| Number | Title | Issue Date |
| 7971044 | Link stack repair of erroneous speculative update Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maint... | 06/28/2011 |
| 7900027 | Scalable link stack control method with full support for speculative operations A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and pops from the link stack. The link stack comprises a set of entries, and ... | 03/01/2011 |
| 7882338 | Method, system and computer program product for an implicit predicted return from a predicted subroutine A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a ... | 02/01/2011 |
| 7836290 | Return address stack recovery in a speculative execution computing apparatus A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order instruction processing, and exception handling. In at least one embodiment... | 11/16/2010 |
| 7793086 | Link stack misprediction resolution A method for link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function returns. The method comprises establishing a set of physical data structure... | 09/07/2010 |
| 7647489 | Function calling mechanism with embedded index for a handler program and an embedded immediate value for passing a parameter A data processing system 2 is provided which includes an instruction decoder 18 responsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler pointer in dependence upon a handler base address HBA and th... | 01/12/2010 |
| 7617388 | Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 11/10/2009 |
| 7581089 | Method of protecting a computer stack A method of protecting a return address on a computer stack is disclosed. Two stacks are created, the first a normal stack, and the second, or shadow, having shadow frames containing the return address upon a subroutine call, the address on the first stack where the... | 08/25/2009 |
| 7478228 | Apparatus for generating return address predictions for implicit and explicit subroutine calls An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and a second input. The second input is configured to receive predecode ... | 01/13/2009 |
| 7444501 | Methods and apparatus for recognizing a subroutine call An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the nex... | 10/28/2008 |
| 7412593 | Processor for processing a program with commands including a mother program and a sub-program A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mot... | 08/12/2008 |
| 7409479 | Semiconductor integrated circuit When needing to make write accesses to both upper and lower sides of a counter in a timer, a CPU accesses the lower side last, and accesses the lower side first when needing to make read accesses thereto. The timer stores data of the data bus in the write buffer at ... | 08/05/2008 |
| 7401210 | Selecting subroutine return mechanisms Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence ... | 07/15/2008 |
| 7386709 | Controlling execution of a block of program instructions within a computer processing system A data processing apparatus is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that block of program instructions. When the end of that block of program instr... | 06/10/2008 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7343482 | Program subgraph identification There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said pro... | 03/11/2008 |
| 7290253 | Prediction mechanism for subroutine returns in binary translation sub-systems of computers A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the retur... | 10/30/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7278137 | Methods and apparatus for compiling instructions for a data processor Methods and apparatus optimized for compiling instructions in a data processor are disclosed. In one aspect, a method of address calculation is disclosed, comprising operating a compiler to generate at least one instruction; canonicalizing the address calculation in... | 10/02/2007 |
| 7237098 | Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address. Typically the return stack is more accurate. However, if the return stack... | 06/26/2007 |
| 7219218 | Vector technique for addressing helper instruction groups associated with complex instructions The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calcu... | 05/15/2007 |
| 7216220 | Microprocessor with customer code store A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA leve... | 05/08/2007 |
| 7203826 | Method and apparatus for managing a return stack A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of retu... | 04/10/2007 |
| 7203827 | Link and fall-through address formation using a program counter portion selected by a specific branch address bit A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second a... | 04/10/2007 |
| 7200740 | Apparatus and method for speculatively performing a return instruction in a microprocessor A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branc... | 04/03/2007 |
| 7200736 | Method and system for substantially registerless processing A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an arithmetic logic unit, an address multiplexer, and a storage multiplexer. The processor utilizes a data stream... | 04/03/2007 |
| 7185338 | Processor with speculative multithreading and hardware to support multithreading software A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to ... | 02/27/2007 |
| 7162621 | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 01/09/2007 |
| 7146442 | Motherboard having a non-volatile memory which is reprogrammable through a video display port A motherboard of a computer system has a video display port, a reprogrammable non-volatile memory, a controller for the non-volatile memory, and a graphics controller circuit for outputting video signals to the video display port. A wired-OR circuit connects the gra... | 12/05/2006 |
| 7130942 | Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a ... | 10/31/2006 |
| 7117069 | Apparatus and method for executing block programs An apparatus for executing a block program includes a block table listing records corresponding to a plurality of blocks in the block program. A block library is included to hold algorithms associated with the blocks. An executing program selectively processes the b... | 10/03/2006 |
| 7103759 | Microcontroller architecture supporting microcode-implemented peripheral devices Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute... | 09/05/2006 |
| 7093099 | Native lookup instruction for file-access processor searching a three-level lookup cache for variable-length keys A processor natively executes lookup instructions. The lookup instruction is decoded to determine which general-purpose register (GPR) contains a pointer to a lookup key in a buffer. A variable-length key is read from the buffer and hashed to generate an index into ... | 08/15/2006 |
| 7069105 | Process module for a handling station, handling station and procedure for the line-up of a handling station A process module for a processing station (18) for performing a predetermined function. The module comprises a controller (60) associated with a program control unit (76; 76′) to which a program for controlling the process module is supplied. ... | 06/27/2006 |
| 6996677 | Method and apparatus for protecting memory stacks Method and apparatus for protecting processing elements from buffer overflow attacks are provided. The apparatus includes a memory stack for, upon execution of a jump to subroutine, storing a return address in a first location in a stack memory. A second location se... | 02/07/2006 |
| 6973563 | Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction Various embodiments of methods and systems for implementing a return address prediction mechanism in a microprocessor are disclosed. In one embodiment, a return address prediction mechanism includes a return storage and a controller. The return storage includes one ... | 12/06/2005 |
| 6970966 | System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which... | 11/29/2005 |
| 6966055 | Optimizing post-link code A method for code optimization includes disassembling object code that has been compiled and linked, and identifying a function in the disassembled code, the function including store and restore instructions with respect to a register. The disassembled code is analy... | 11/15/2005 |
| 6954849 | Method and system to use and maintain a return buffer An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction... | 10/11/2005 |
| 6948005 | Peripheral device for programmable controller A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying consecutive devices present in a sequence program, expands devices o... | 09/20/2005 |
