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| Number | Title | Issue Date |
| 8185725 | Selective powering of a BHT in a processor having variable length instructions In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are f... | 05/22/2012 |
| 8151097 | Multi-threaded system with branch When two threads (strands), for example, are executed in parallel in a processor in a simultaneous multi-thread (SMT) system, entries of a branch reservation station of an instruction control device are separately used in a strand 0 group and a strand 1 | 04/03/2012 |
| 8140833 | Implementing polymorphic branch history table reconfiguration A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration... | 03/20/2012 |
| 8086831 | Indexed table circuit having reduced aliasing In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of diff... | 12/27/2011 |
| 8078852 | Predictors with adaptive prediction threshold An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter ... | 12/13/2011 |
| 8078851 | Processor and method for recovering global history shift register and return address stack thereof by determining a removal range of a branch recovery table A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. ... | 12/13/2011 |
| 7975133 | Method for repairing a speculative global history record A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch... | 07/05/2011 |
| 7941654 | Local and global branch prediction information storage Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch prediction information, a second table for storing global branch prediction in... | 05/10/2011 |
| 7904705 | System and method for repairing a speculative global history record A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch... | 03/08/2011 |
| 7877587 | Branch prediction within a multithreaded processor A branch prediction mechanism 16, 18 within a multithreaded processor having hardware scheduling logic 6, 8, 10, 12 uses a shared global history table 18 which is indexed by respective branch history registers 20, 22 for each program thre... | 01/25/2011 |
| 7873819 | Branch target buffer addressing in a data processor A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current fetch group address resulting in a group hit in the BTB, the BTB provi... | 01/18/2011 |
| 7849299 | Microprocessor system for simultaneously accessing multiple branch history table entries using a single port Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed f... | 12/07/2010 |
| 7844806 | Global history branch prediction updating responsive to taken branches A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation wi... | 11/30/2010 |
| 7844807 | Branch target address cache storing direct predictions In at least one embodiment, a processor includes at least one execution unit and instruction sequencing logic that fetches instructions for execution by the execution unit. The instruction sequencing logic includes branch logic that outputs predicted branch target a... | 11/30/2010 |
| 7831817 | Two-level branch prediction apparatus A two-level branch prediction apparatus includes branch bias logic for predicting whether a branch instruction will result in a branch being taken. Upon receipt of a first address portion of a branch instruction's address, a first store outputs a corresponding first... | 11/09/2010 |
| 7805595 | Data processing apparatus and method for updating prediction data based on an operation's priority level A data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry includes a history stor... | 09/28/2010 |
| 7797521 | Method, system, and computer program product for path-correlated indirect address predictions A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the gener... | 09/14/2010 |
| 7752426 | Processes, circuits, devices, and systems for branch prediction and other processor improvements A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and ope... | 07/06/2010 |
| 7716460 | Effective use of a BHT in processor having variable length instruction set execution modes In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are f... | 05/11/2010 |
| 7707398 | System and method for speculative global history prediction updating A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch... | 04/27/2010 |
| 7673124 | Filtered branch-prediction predicate generation A method, of manipulating a raw branch history (RBH), can include: providing a RBH relevant to a conditional branching instruction in a program; and filtering the RBH to obtain a filtered branch-prediction predicate. A related method, of making a branch prediction, ... | 03/02/2010 |
| 7657729 | Efficient multiple-table reference prediction mechanism A method and an apparatus for enabling a prefetch engine to detect and support hardware prefetching with different streams in received accesses. Multiple (simple) history tables are provided within (or associated with) the prefetch engine. Each of the multiple table... | 02/02/2010 |
| 7647488 | Information processing device with branch history restoration The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, ev... | 01/12/2010 |
| 7624258 | Using computation histories to make predictions Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not limited to) registers, memory locations, static values, and instruction pr... | 11/24/2009 |
| 7500088 | Methods and apparatus for updating of a branch history table Methods and apparatus are provided for enhanced instruction handling in processing environments. If branch misprediction occurs during instruction processing, a branch history table may be updated based upon the number of instructions to be fetched. The branch histo... | 03/03/2009 |
| 7493480 | Method and apparatus for prefetching branch history information A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very fast) first level branch history table (L1 BHT) before the processor ... | 02/17/2009 |
| 7472264 | Predicting a jump target based on a program counter and state information for a process One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and use... | 12/30/2008 |
| 7454602 | Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a branch history table. The GBH buffer contains GBH information of a gro... | 11/18/2008 |
| 7447885 | Reading prediction outcomes within a branch prediction mechanism A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to... | 11/04/2008 |
| 7437543 | Reducing the fetch time of target instructions of a predicted taken branch instruction A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instru... | 10/14/2008 |
| 7430657 | System, method and device for queuing branch predictions A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A look up may be made of for example two sequential lines, and for exampl... | 09/30/2008 |
| 7428632 | Branch prediction mechanism using a branch cache memory and an extended pattern cache A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they ... | 09/23/2008 |
| 7428627 | Method and apparatus for predicting values in a processor having a plurality of prediction modes A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor comprising a per-IP (“PIP”) table and a next value table. The PIP tabl... | 09/23/2008 |
| 7426628 | Run-time node prefetch prediction in dataflow graphs A method for run-time prediction of a next caller of a shared functional unit, wherein the shared functional unit is operable to be called by two or more callers out of a plurality of callers. The shared functional unit and the plurality of callers are operable to e... | 09/16/2008 |
| 7426631 | Methods and systems for storing branch information in an address table of a processor Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address t... | 09/16/2008 |
| 7418583 | Data dependency detection using history table of entry number hashed from memory address A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence... | 08/26/2008 |
| 7409535 | Branch target prediction for multi-target branches by identifying a repeated pattern An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-ta... | 08/05/2008 |
| 7380110 | Branch prediction structure with branch direction entries that share branch prediction qualifier entries An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst multiple entries of the first portion. In this way, overall storage (and ... | 05/27/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7370183 | Branch predictor comprising a split branch history shift register An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system conte... | 05/06/2008 |
