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| Number | Title | Issue Date |
| 7984279 | System and method for using a working global history register A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identifi... | 07/19/2011 |
| 7925870 | Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The entry designation unit computes a designate entry position in a return a... | 04/12/2011 |
| 7797520 | Early branch instruction prediction A data processing apparatus including a prefetch unit for prefetching the instructions from a memory, branch prediction logic and a branch target cache for storing predetermined information about branch operations executed by the processor. The information includes ... | 09/14/2010 |
| 7793085 | Memory control circuit and microprocessory system for pre-fetching instructions A memory control circuit for providing a small-circuit-size memory control circuit capable of reducing a branch penalty during the execution of a branch instruction in a CPU. A branch-destination buffer caches a branch-destination instruction and a branch-destinatio... | 09/07/2010 |
| 7783868 | Instruction fetch control device and method thereof with dynamic configuration of instruction buffers This is an instruction fetch control device supplying instructions to an instruction execution unit. The device comprises a plurality of instruction buffers storing an instruction string to be supplied to the instruction execution unit and a designation unit designa... | 08/24/2010 |
| 7734901 | Processor core and method for managing program counter redirection in an out-of-order processor pipeline A processor core and method for managing program counter redirection in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline c... | 06/08/2010 |
| 7702888 | Branch predictor directed prefetch An apparatus for executing branch predictor directed prefetch operations. During operation, a branch prediction unit may provide an address of a first instruction to the fetch unit. The fetch unit may send a fetch request for the first instruction to the instruction... | 04/20/2010 |
| 7685410 | Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirects In one embodiment, a processor comprises a branch resolution unit and a redirect recovery cache. The branch resolution unit is configured to detect a mispredicted branch operation, and to transmit a redirect address for fetching instructions from a correct target of... | 03/23/2010 |
| 7552318 | Branch lookahead prefetch for microprocessors A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pe... | 06/23/2009 |
| 7516312 | Presbyopic branch target prefetch method and apparatus An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch ... | 04/07/2009 |
| 7472262 | Methods and apparatus to prefetch memory objects by predicting program states based on entropy values Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with respective ones of the program states; identifying at least one next probable... | 12/30/2008 |
| 7447881 | Branch prediction apparatus and method A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the offset are added to obtain a branch instruction address, the branch instru... | 11/04/2008 |
| 7441110 | Prefetching using future branch path information derived from branch prediction A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while... | 10/21/2008 |
| 7424578 | Computer system, compiler apparatus, and operating system A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and a thread process creation device. The compiler apparatus creates thr... | 09/09/2008 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified ... | 09/02/2008 |
| 7418526 | Memory hub and method for providing memory sequencing hints A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses ... | 08/26/2008 |
| 7418554 | Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l... | 08/26/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7370153 | System and method of pre-fetching using an extended data structure including required data and a pre-fetch flag Method and apparatus for implementing controlled pre-fetching of data. An extended data structure can be used to specifying where and when data is to be pre-fetched, and how much pre-fetching is to be performed, if any. The extended data structure has a pre-fetch fl... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7353500 | Suppressing execution of monitoring measurement program pointed to by inserted branch after threshold number of coverage to reduce instruction testing overhead In a method for testing a program, repeated measurement on branches that are frequently taken is prevented, thereby avoiding unnecessary overhead. An information processing device includes a coverage measurement control program for determining whether the number of ... | 04/01/2008 |
| 7353505 | Tracing the execution path of a computer program The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one ... | 04/01/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to proce... | 03/25/2008 |
| 7328332 | Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740)... | 02/05/2008 |
| 7315934 | Data processor and program for processing a data matrix A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit... | 01/01/2008 |
| 7310748 | Memory hub tester interface and method for use thereof A memory hub including a memory test bridge circuit for testing memory devices. Test command packets are coupled from a tester to the memory hub responsive to a test clock signal having a test clock frequency. The test bridge circuit generates memory device command,... | 12/18/2007 |
| 7310752 | System and method for on-board timing margin testing of memory modules A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link int... | 12/18/2007 |
| 7293161 | Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for exe... | 11/06/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7282947 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 10/16/2007 |
| 7281120 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an inter... | 10/09/2007 |
| 7281122 | Method and apparatus for nested control flow of instructions using context information and instructions having extra bits A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further incl... | 10/09/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7278013 | Apparatus having a cache and a loop buffer Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core. ... | 10/02/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7272682 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/18/2007 |
| 7266676 | Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array,... | 09/04/2007 |
