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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Number | Title | Issue Date |
| 5933628 | Method for identifying hard-to-predict branches to enhance processor performance A method and apparatus for handling branch instructions contained within a source program includes applying a set of heuristics to classify each of the branch instructions in the source program as either a hard-to-predict type or a simple type of branch. ... | 08/03/1999 |
| 5933644 | Method and apparatus for conflict-based block reordering A method and apparatus for ordering blocks of code by a compiler. The compiler generates a conflict graph in accordance with the blocks of a computer program being compiled. Once the conflict graph is generated, a preferred embodiment of the present inven... | 08/03/1999 |
| 5923863 | Software mechanism for accurately handling exceptions generated by instructions scheduled speculatively due to branch elimination Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a specul... | 07/13/1999 |
| 5881276 | Manipulation of protected pages to reduce conditional statements A method and apparatus to reduce conditional statements in normal code flow. A plurality of contiguous memory pages are allocated as either protected or unprotected. A pointer is defined to point to an address such that an operation (write or read) to an ... | 03/09/1999 |
| 5872964 | Comparison operating unit and graphic operating system A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on tw... | 02/16/1999 |
| 5870598 | Method and apparatus for providing an optimized compare-and-branch instruction An optimized compare-and-branch instruction for execution in a RISC type microprocessor. An instruction sequencer implemented in the microprocessor is responsive to a compare-and-branch instruction for efficient execution. The instruction sequencer detect... | 02/09/1999 |
| 5867699 | Instruction flow control for an instruction processor Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect instruction by the pipelined instruction processor provides a ... | 02/02/1999 |
| 5850553 | Reducing the number of executed branch instructions in a code sequence A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming ex... | 12/15/1998 |
| 5838961 | Method of operation and apparatus for optimizing execution of short instruction branches A technique for speeding CPU operations in handling branch instructions in which the target instructions is a short displacement away from its branch instruction is disclosed. When the target instruction is displaced within a predetermined number of instr... | 11/17/1998 |
| 5826074 | Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register A processor has 64-bit operand execution pipelines, but a 32-bit branch pipeline. The branch pipeline contains registers to hold the lower 32-bit sub-addresses of 64-bit target and sequential addresses for conditional branches which have been predicted bu... | 10/20/1998 |
| 5819080 | Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register override prefix byte which may be included with the instruction.... | 10/06/1998 |
| 5815699 | Configurable branch prediction for a processor performing speculative execution In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in softwa... | 09/29/1998 |
| 5815701 | Computer method and apparatus which maintains context switching speed with a large number of registers and which improves interrupt processing time Registers are divided into a global pool and a local pool. Code to be used in the processor must allocate registers from the global pool for values that live across decision trees and from the local pool for local values. The processor only accepts interr... | 09/29/1998 |
| 5815695 | Method and apparatus for using condition codes to nullify instructions based on results of previously-executed instructions on a computer processor The invention is a method and apparatus for conditionally nullifying a current instruction based on a first test value where the first test value can be set in one or more prior instructions and where the execution of the current instruction can set a sec... | 09/29/1998 |
| 5809294 | Parallel processing unit which processes branch instructions without decreased performance when a branch is taken A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in the branch-delay slot are those fetched in a period from fet... | 09/15/1998 |
| 5805876 | Method and system for reducing average branch resolution time and effective misprediction penalty in a processor Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the ... | 09/08/1998 |
| 5802337 | Method and apparatus for executing load instructions speculatively A load is executed speculatively as a dismissible load instruction, which does not take exceptions, and a check instruction, which is in the same format as the dismissible load, that when executed determines whether an exception should be taken on the dis... | 09/01/1998 |
| 5799180 | Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken Circuits, systems, and methods relating to processor which processes a plurality of sequentially arranged instructions. In the method, one method step (10) receives into a processor pipeline an instruction from the plurality of sequentially arranged instr... | 08/25/1998 |
| 5799179 | Handling of exceptions in speculative instructions CPU overhead is minimized through tracking speculative exceptions (202) for later processing during exception resolution (204) including pointing to the addresses of these speculative instructions, and resolving (204) these exceptions by correcting (206) ... | 08/25/1998 |
| 5797025 | Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates... | 08/18/1998 |
| 5796997 | Fast nullify system and method for transforming a nullify function into a select function A fast nullify system and method facilitate handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch mechanism to a reordering mechanism, where the instructions are... | 08/18/1998 |
| 5794025 | Method and device for performing modulo-based arithmetic operations in an asynchronous transfer mode cell processing system Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a modulo arithmetic feature which permits branching on the modulo portion of the result of an arithmetic operation. An a... | 08/11/1998 |
| 5787276 | Microprocessor including circuit for generating signal used for tracing executed instruction stream A microprocessor which is constructed to output outside a pipeline flash signal in response to a branch caused by a conditional branch instruction being to be taken, includes a decoder unit decoding and producing decoded information of each of instruction... | 07/28/1998 |
| 5784603 | Fast handling of branch delay slots on mispredicted branches An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot instructions. When a mispredicted branch occurs, all inst... | 07/21/1998 |
| 5770894 | Parallel processing method having arithmetical conditions code based instructions substituted for conventional branches A computer implemented method performed by a processor having multiple functional units avoids branches in decision support codes by doing arithmetic instructions incorporating condition codes generated by compare instructions. The method comprising the s... | 06/23/1998 |
| 5768593 | Dynamic cross-compilation system and method In a computer system, a cross-compiler converts non-native code into native code immediately prior to execution of that code. The system also includes a code cache for storing cross-compiled code and a hash table for locating code blocks in the code cache... | 06/16/1998 |
| 5758142 | Trainable apparatus for predicting instruction outcomes in pipelined processors A predictor which chooses between two or more predictors is described. The predictor includes a first component predictor which operates according to a first algorithm to produce a prediction of an action and a second component predictor which operates ac... | 05/26/1998 |
| 5748976 | Mechanism for maintaining data coherency in a branch history instruction cache A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target ins... | 05/05/1998 |
| 5740458 | Protocol processor intended for the execution of a collection of instructions in a reduced number of operations Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation reg... | 04/14/1998 |
| 5740415 | Instruction supplying apparatus with a branch target buffer having the contents so updated as to enhance branch prediction accuracy A branch execution unit processes operand data which is supplied from an instruction decoder with branch instruction information which is read from a branch target buffer, carries out branch prediction and execution, and forms a branch probability flag wh... | 04/14/1998 |
| 5737561 | Method and apparatus for executing an instruction with multiple brancing options in one cycle A multi-alternative structure, such as a case instruction, in a computer system that can be executed in one cycle. The computer system of the present invention executes multiple instructions, wherein condition indicators are set according to the execution... | 04/07/1998 |
| 5729728 | Method and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessor A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redi... | 03/17/1998 |
| 5729707 | Instruction prefetch circuit and cache device with branch detection In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is actually executed. Accordingly, when the branch instruction is a conditional branch instruction and not actuall... | 03/17/1998 |
| 5724564 | Computer program product and program storage device for representing and signaling run-time program conditions An improved method and system is described for generalized handling of conditions occurring during program execution in a computer system having a multi-language Condition Manager (CM). A general signaling routine having object code for an external entry ... | 03/03/1998 |
| 5721927 | Method for verifying contiquity of a binary translated block of instructions by attaching a compare and/or branch instruction to predecessor block of instructions A method for enabling a first block of instructions to verify whether the first block of instructions follows a second block of instructions in an order of execution. The method includes appending a compare instruction to the first block of instructions. ... | 02/24/1998 |
| 5706490 | Method of processing conditional branch instructions in scalar/vector processor A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache... | 01/06/1998 |
| 5706491 | Branch processing unit with a return stack including repair using pointers from different pipe stages A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return stack for call/returns, including return stack pointer repa... | 01/06/1998 |
| 5694617 | System for prioritizing quiesce requests and recovering from a quiescent state in a multiprocessing system with a milli-mode operation A milli-mode routine handles a quiesce interrupt, and causes all the processors in the system to enter a quiesced state. A single bit of a millicode control register indicates a quiesced state and drives an output of the processor to indicate the processo... | 12/02/1997 |
| 5689694 | Data processing apparatus providing bus attribute information for system debugging The data processing apparatus which outputs information regarding the prefetching of an instruction in the destination of a branch instruction prior to the confirmation of its branch condition. The apparatus uses the output information to delete unexecute... | 11/18/1997 |
| 5689695 | Conditional processor operation based upon result of two consecutive prior processor operations This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set ... | 11/18/1997 |
