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| Number | Title | Issue Date |
| 8161274 | Command selection method and its apparatus When selecting one command within a processor from a plurality of command queues vested with order of priority, the order of priority assigned to the plurality of command queues is dynamically changed so as to select a command, on a priority basis, from a command qu... | 04/17/2012 |
| 8145890 | Pipelined microprocessor with fast conditional branch instructions based on static microcode-implemented instruction state A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fe... | 03/27/2012 |
| 8131984 | Pipelined microprocessor with fast conditional branch instructions based on static serializing instruction state A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in th... | 03/06/2012 |
| 8086830 | Arithmetic processing apparatus An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic pr... | 12/27/2011 |
| 8078849 | Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-w... | 12/13/2011 |
| 8019776 | Determining device and determining method for determining processing to be performed based on acquired data The present invention provides a technique for determining processing to be performed at high speed. When processing to be performed is determined through multiple condition judgments and branches, a comparison target extraction circuit extracts from acquired data m... | 09/13/2011 |
| 7975132 | Apparatus and method for fast correct resolution of call and return instructions using multiple call/return stacks in the presence of speculative conditional instruction execution in a pipelined microprocessor A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and d... | 07/05/2011 |
| 7930526 | Compare and branch mechanism A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target br... | 04/19/2011 |
| 7886133 | Information processing apparatus and method for accelerating information processing An apparatus comprises an instruction execution control unit which fetches an instruction executed according to a microinstruction, the instruction is classified into a plurality of types, from a memory, wherein the types include a first type indicative of generatin... | 02/08/2011 |
| 7877586 | Branch target address cache selectively applying a delayed hit In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one exe... | 01/25/2011 |
| 7861071 | Conditional branch instruction capable of testing a plurality of indicators in a predicate register A method of conditionally executing branch instructions which comprise an opcode field defining a type of test to be applied to determine whether or not to execute a branch operation, a control field designating a control store holding a plurality of indicators and ... | 12/28/2010 |
| 7797519 | Processor apparatus with instruction set for storing comparison conditions and for evaluating branch condition values against results of identified complex comparison conditions There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or eac... | 09/14/2010 |
| 7783867 | Controlling instruction execution in a processing environment Instruction execution is controlled by a single test that determines whether processing should continue in mainline processing or fall through to a test set. The single test compares a dynamically set variable to an instruction counter. If the test is met, mainline ... | 08/24/2010 |
| 7779240 | System and method for reducing power consumption in a data processor having a clustered architecture There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, ... | 08/17/2010 |
| 7725694 | Processor, microcomputer and method for controlling program of microcomputer A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a condit... | 05/25/2010 |
| 7721075 | Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instru... | 05/18/2010 |
| 7721073 | Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses A RISC processor having a data moving engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instr... | 05/18/2010 |
| 7721074 | Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses A RISC processor having a data mover engine and instructions that associate register addresses with memory addresses. In an embodiment, the instructions include a read-tie instruction, a single write-tie instruction, a dual write-tie instruction, and an untie instru... | 05/18/2010 |
| 7716459 | Protection of a program jump from fault injection by masking a memory address with a random number A method for performing at least one jump in a program executed by a processor, including determining a result over several bits as an indicator that a desired condition has been complied with, the result corresponding to an operation taking into account at least on... | 05/11/2010 |
| 7634644 | Effective elimination of delay slot handling from a front section of a processor pipeline Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline f... | 12/15/2009 |
| 7634643 | Stack register reference control bit in source operand of instruction A processor is disclosed herein that may execute an instruction that includes an immediate value and a reference to a register accessible to the processor. The instruction causes the processor to perform a test using the immediate value and the contents of the regis... | 12/15/2009 |
| 7603545 | Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching An instruction control method carries out an instruction in a processor to process instructions by out-of-order processing, using delay instructions for branching. The processor includes a storage unit, a branch predictor making branch predictions and a control unit... | 10/13/2009 |
| 7600102 | Condition bits for controlling branch processing A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, the condition bits being adapt... | 10/06/2009 |
| 7581088 | Conditional execution using an efficient processor flag Methods and apparatus are provided for optimizing a conditional execution on a processor core. A processor sets a flag based on both the result and the type of an instruction. The flag is used during evaluation of a subsequent instruction to determine if the subsequ... | 08/25/2009 |
| 7434036 | System and method for executing software program instructions using a condition specified within a conditional execution instruction A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional execution instruction specifies one or more instructions to be conditi... | 10/07/2008 |
| 7428632 | Branch prediction mechanism using a branch cache memory and an extended pattern cache A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they ... | 09/23/2008 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified ... | 09/02/2008 |
| 7418578 | Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution instruction group includes a conditional execution instruction and a co... | 08/26/2008 |
| 7415602 | Apparatus and method for processing a sequence of jump instructions An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining t... | 08/19/2008 |
| 7406613 | Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whe... | 07/29/2008 |
| 7398373 | System and method for processing complex computer instructions A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instructio... | 07/08/2008 |
| 7389405 | Digital signal processor architecture with optimized memory access for code discontinuity A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time ... | 06/17/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370181 | Single stepping a virtual machine guest using a reorder buffer Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder buffer. The sequencer is to issue micro-operations. The reorder buff... | 05/06/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7363419 | Method and system for terminating write commands in a hub-based memory system A memory hub receives downstream memory commands and processes each received downstream memory command to determine whether the memory command includes a write command directed to the memory hub. The memory hub operates in a first mode when the write command is dire... | 04/22/2008 |
| 7353320 | Memory hub and method for memory sequencing A memory module includes a memory hub coupled to several memory devices. The memory hub includes at least one performance counter that tracks one or more system metrics—for example, page hit rate, prefetch hits, and/or cache hit rate. The performance counter commu... | 04/01/2008 |
| 7353369 | System and method for managing divergent threads in a SIMD architecture One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetchin... | 04/01/2008 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to proce... | 03/25/2008 |
