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...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
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| Number | Title | Issue Date |
| 7444500 | Method for executing a 32-bit flat address program during a system management mode interrupt A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine initially saves the state of the processor and then executes an instr... | 10/28/2008 |
| 7389407 | Central control system and method for using state information to model inflight pipelined instructions A method and apparatus to control logic sections of a pipeline instruction processor is disclosed. A state machine is provided that models the flow of instructions through the pipeline. The state machine is capable of modeling execution for all combinations of instr... | 06/17/2008 |
| 7348799 | System and method for generating a trigger signal One disclosed embodiment may comprise an application specific integrated circuit (ASIC). The ASIC includes memory that stores condition data defining conditions for enabling transitions among a plurality of states and next state data defining a next state associated... | 03/25/2008 |
| 7277920 | Implementing applications requiring access to multiple files The control flow underlying an application is represented in the form of a FSM (Finite State Machine) containing multiple states, transitions between states, and tasks associated with each transition. An execution block iteratively (in loops) transitions between the... | 10/02/2007 |
| 6990570 | Processor with a computer repeat instruction A processing engine, such as a digital signal processor, includes an execution mechanism, a repeat count register and a repeat count index register. The execution mechanism is operable for a repeat instruction to initialize the repeat count index register with the c... | 01/24/2006 |
| 6865425 | State machine for a pulse output function At least one exemplary embodiment comprises a system comprising an arithmetic logic unit; a memory comprising a pre-computed table of target pulse widths, changes in pulse width, and pulse counts distributed according to a constrained semi-logarithmic distribution, ... | 03/08/2005 |
| 6775832 | Method and apparatus for a layer structure directory for common hardware interface modules An invention is disclosed for a layer structure that facilitates configuring a Fiber Channel driver. In one embodiment, the layer structure includes a hardware layer directory that includes code for communicating with a Fiber Channel controller. In addition, a wrapp... | 08/10/2004 |
| 6757818 | Programmable microcontroller for controlling multichannel sequences of states to be processed in each processing period A programmable controller for controlling a multi-channel sequential processing of states based on a prescribed state transitions. The microcontroller has a state register for each of the channels for holding the state data to be processed in the channel in the next... | 06/29/2004 |
| 6643770 | Branch misprediction recovery using a side memory A mispredicted path side memory is configured to be coupled to a stage in an instruction pipeline. As instructions advance through the pipeline, a result from the stage is stored into the mispredicted path side memory. The result is restored from the misp... | 11/04/2003 |
| 6505294 | Direct control of operation blocks using operand signal of control instruction as extension to instruction set in a hardwired control processor A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For a special control instruction, the operand section is transmitted to the operation blocks along a bypass path separate from the norm... | 01/07/2003 |
| 6381328 | ETSI intelligent network capability set 1 intelligent network application protocol service switching point finite state machine A finite state machine that implements the ETSI Intelligent Network Capability Set 1 for INAP protocol using a first finite state machine connected to a second finite state machine. To accomplish this implementation, the first finite state machine receive... | 04/30/2002 |
| 6279068 | Set of two memories on the same monolithic integrated circuit Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided ... | 08/21/2001 |
| 6223277 | Data processing circuit with packed data structure capability A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to an input of each of a plurality of operand multiplexers (... | 04/24/2001 |
| 6219723 | Method and apparatus for moderating current demand in an integrated circuit processor A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the... | 04/17/2001 |
| 6216221 | Method and apparatus for expanding instructions A microprocessor includes a decoder, a queue, and a renamer. The decoder is adapted to receive a program instruction and decode the program instruction to provide a first decoded instruction. The first decoded instruction includes a plurality of instructi... | 04/10/2001 |
| 6205512 | Set of two memories on the same monolithic integrated circuit Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided ... | 03/20/2001 |
| 5964866 | Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the st... | 10/12/1999 |
| 5948106 | System for thermal overload detection and prevention for an integrated circuit processor A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the... | 09/07/1999 |
| 5940006 | Enhanced uplink modulated backscatter system A Time Division Multiple Access (TDMA) duplex radio communication system uses an Interrogator to generate a first radio signal by modulating a first information signal onto a radio carrier signal which is sent to at least one remote Tag of the system. The... | 08/17/1999 |
| 5937177 | Control structure for a high-speed asynchronous pipeline Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits. When a full control circuit precedes an empty control circuit in the chain, indicating that t... | 08/10/1999 |
| 5826096 | Minimal instruction set computer architecture and multiple instruction issue method A minimal instruction set computer architecture (hyperscalar computer architecture) comprises a central memory, an instruction buffer, a control unit, an I/O control unit, a plurality of functional units, a plurality of register files, and a data router. ... | 10/20/1998 |
| 5623680 | Finite state machine for process control A model of a finite state machine suited for implementation in a microcomputer includes logical specifications stored in memory which determine whether a change of outputs should be effected in response to predetermined combinations of input parameters an... | 04/22/1997 |
| 5600845 | Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor An integrated circuit computing device is comprised of a dynamically configurable Field Programmable Gate Array (FPGA). This gate array is configured to implement a RISC processor and a Reconfigurable Instruction Execution Unit. Since the FPGA can be dyna... | 02/04/1997 |
| 5588118 | Single chip dual processor A single chip dual processor is implemented combining a microcontroller and digital signal processor. An unitary instruction set is utilized for programming both processors in one source program which is stored in a single external program memory. While c... | 12/24/1996 |
| 5519873 | Apparatus for switching digital command execution between a general purpose microprocessor and dedicted execution logic Apparatus for transferring control of digital command execution from dedicated digital logic to an off chip microprocessor. A command register receives said digital commands. A decoder connected to the command register will be connected via a decoded comm... | 05/21/1996 |
| 4697250 | Flexible computer control unit Disclosed is a control unit including a flexible decoder unit providing control patterns for controlling functional units in data processing equipment. The control unit includes hardwired decoder logic which decodes a multi-bit key to provide primary deco... | 09/29/1987 |
| 4575794 | Clocking mechanism for multiple overlapped dynamic programmable logic arrays used in a digital control unit A clocking mechanism is provided for multiple overlapped dynamic programmable logic arrays which are used in a digital control unit wherein a sequence of control words are used to produce successive groups of control point signals. Such a control unit inc... | 03/11/1986 |
| 4179736 | Microprogrammed computer control unit capable of efficiently executing a large repertoire of instructions for a high performance data processing unit A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and secon... | 12/18/1979 |
| 4161026 | Hardware controlled transfers to microprogram control apparatus and return via microinstruction restart codes A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an a... | 07/10/1979 |
