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| Number | Title | Issue Date |
| 6920548 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out... | 07/19/2005 |
| 6920531 | Method and apparatus for updating and invalidating store data In a computer architecture using a prevalidated tag cache design, logic circuits are added to enable store and invalidation operations without impacting integer load data access times and to invalidate stale cache lines. The logic circuits include a translation look... | 07/19/2005 |
| 6918119 | Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments The present invention relates to a method and system for determining the status of each entry in an instruction window buffer in multi-processor, parallel processing environments. A combinatorial circuit, which automatically generates active instruction window statu... | 07/12/2005 |
| 6915416 | Apparatus and method for microcontroller debugging Apparatus and method for microcontroller debugging. A preferred embodiment microcontroller integrated circuit comprises debug circuitry on the integrated circuit. The debug circuitry is capable of breaking normal instruction execution based on an address breakpoint,... | 07/05/2005 |
| 6915412 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 07/05/2005 |
| 6912640 | Method to partition large code across multiple e-caches A method for executing an instruction stream includes partitioning the instruction stream using a partition point to obtain a first partition of the instruction stream and a second partition of the instruction stream, configuring the first partition and the second p... | 06/28/2005 |
| 6912648 | Stick and spoke replay with selectable delays A method for stick and spoke replay in a processor. The method of one embodiment comprises dispatching an instruction for execution. The instruction is speculatively executed. It is determined whether the instruction executed correctly. The instruction is routed to ... | 06/28/2005 |
| 6910123 | Processor with conditional instruction execution based upon state of corresponding annul bit of annul code A processor having a changeable architected state. The processor includes an instruction memory for storing instructions. The processor also includes an instruction pipeline, where an instruction which passes entirely through the pipeline alters the architected stat... | 06/21/2005 |
| 6910109 | Tracking memory page state The present invention is a method and apparatus for tracking a state of a page of a memory device which has at least a dependent bank structure. A page entry table contains attribute entries of the page. An access control circuit generates access information and a c... | 06/21/2005 |
| 6907515 | Configuration control within data processing systems A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data 310, 312, 314, 316 | 06/14/2005 |
| 6895497 | Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority A multiple dispatch processor has several instruction fetch units, each for providing a stream of instructions to an instruction decode and dispatch unit. The processor also has an resource allocation unit, and multiple resources such as combined integer and address... | 05/17/2005 |
| 6880067 | Retiring instructions that meet the early-retirement criteria to improve computer operation throughput Techniques are provided for retiring instructions that typically complete early as compared to most instructions. In an embodiment, all instructions are processed normally until the instruction queue is full. At that time, the system is frozen, e.g., all units stop ... | 04/12/2005 |
| 6862676 | Superscalar processor having content addressable memory structures for determining dependencies A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies betwe... | 03/01/2005 |
| 6832117 | Processor core for using external extended arithmetic unit efficiently and processor incorporating the same A processor core for realizing efficient operation processing by connecting an extended arithmetic unit to its exterior and a processor incorporating such a processing core are provided. The processor includes the processor core, a data memory accessed by the proces... | 12/14/2004 |
| 6829699 | Rename finish conflict detection and recovery An improved method and system for operating an out of order processor at a high frequency enabled by an increased pipeline length. It is proposed to shorten the pipeline by a considerable number of stages by accepting that a write after read conflict may occur, when... | 12/07/2004 |
| 6820188 | Method and apparatus for varying instruction streams provided to a processing device using masks A circuit is provided to provide instruction streams to a processing device: embodiments of the circuit are appropriate for use with RISC CPUs, whereas other embodiments are useable with other processing devices, such as small processing devices used in a field prog... | 11/16/2004 |
| 6813702 | Methods and apparatus for generating effective test code for out of order super scalar microprocessors A technique for producing a test executable in a computer. The technique involves forming multiple instruction streams. The technique further involves dividing the multiple instruction streams into portions, and generating a combined instruction stream having the po... | 11/02/2004 |
| 6807621 | Pipelined microprocessor and a method relating thereto A pipelined microprocessor for processing instructions includes at least one pipeline. The pipeline includes and instruction fetching functional stage, an instruction decoding functional stage, an execution functional stage comprising a number of execution units and... | 10/19/2004 |
| 6801202 | Graphics system configured to parallel-process graphics data using multiple pipelines A method and computer graphics system capable of implementing multiple pipelines for the parallel processing of graphics data. For certain data, a requirement may exist that the data be processed in order. The graphics system may use a set of tokens to reliably swit... | 10/05/2004 |
| 6799157 | Method for improving pin compatibility in microcomputer emulation equipment An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation m... | 09/28/2004 |
| 6792523 | Processor with instructions that operate on different data types stored in the same single logical register file A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears t... | 09/14/2004 |
| 6789100 | Interstream control and communications for multi-streaming digital processors A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other ... | 09/07/2004 |
| 6779104 | Method and apparatus for pre-processing instructions for a processor Method and apparatus for reducing or eliminating retirement logic in an out-of-order processor are disclosed. Instructions are processed using a processing unit capable of out-of-order processing and having architectural registers having an architectural state. Grou... | 08/17/2004 |
| 6760836 | Apparatus for issuing an instruction to a suitable issue destination An instruction issuing device comprises a plurality of issue controlling circuits which run in parallel, and perform a control for preferentially issuing an instruction to a particular arithmetic unit. An optimum issue controlling circuit is selected according to th... | 07/06/2004 |
| 6757808 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags whi... | 06/29/2004 |
| 6757807 | Explicitly clustered register file and execution unit architecture A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Regist... | 06/29/2004 |
| 6754892 | Instruction packing for an advanced microprocessor A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of portions representing constraints, operating on the initial value of... | 06/22/2004 |
| 6745318 | Method and apparatus of configurable processing An apparatus that provides configurable processing includes a fetch module, a decoder, and a dynamic arithmetic unit. The fetch module is operable to fetch at least one instruction and provide it to the decoder. The decoder receives the instruction and decodes it. T... | 06/01/2004 |
| 6742110 | Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution A processing engine 10 for executing instructions in parallel comprises an instruction buffer 600 for holding at least two instructions, with the first instruction 602 in a first position and the second instruction 604 in a second positio... | 05/25/2004 |
| 6742108 | Method and apparatus for executing load instructions speculatively A load is executed speculatively as a dismissible load instruction, which does not take exceptions, and a check instruction, which is in the same format as the dismissible load, that when executed determines whether an exception should be taken on the dismissible lo... | 05/25/2004 |
| 6742111 | Reservation stations to increase instruction level parallelism A data processing system having a distributed reservation station is provided which stores basic blocks of code in the form of microprocessor instructions. The present invention is capable of distributing basic blocks of code to the various distributed reservation s... | 05/25/2004 |
| 6735688 | Processor having replay architecture with fast and slow replay paths According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism ... | 05/11/2004 |
| 6735685 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose i... | 05/11/2004 |
| 6728865 | Pipeline replay support for unaligned memory operations Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is synchronized to the instruction pipeline. At the executio... | 04/27/2004 |
| 6725362 | Method for encoding an instruction set with a load with conditional fault instruction The present invention relates to a method and system for providing a load with conditional fault instruction that includes an associated conditional operator, which enables load operations to be advanced above program branches by the compiler without causing unwarra... | 04/20/2004 |
| 6725359 | Address stage logic for generating speculative address operand interim results of preceding instruction by arithmetic operations and configuring An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preced... | 04/20/2004 |
| 6725355 | Arithmetic processing architecture having a portion of general-purpose registers directly coupled to a plurality of memory banks A microprocessor having an internal memory for storing data to be process, a data pointer register for storing an address on the internal memory, a decoder 36 for decoding an instruction, a general-purpose register module 11 including data registers r | 04/20/2004 |
| 6721873 | Method and apparatus for improving dispersal performance in a processor through the use of no-op ports A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal ... | 04/13/2004 |
| 6718458 | Method and apparatus for performing addressing operations in a superscalar, superpipelined processor A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform address... | 04/06/2004 |
| 6714961 | Multiple job signals per processing unit in a multiprocessing system The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to the processing unit for speculative execution of a corresponding fir... | 03/30/2004 |
