Class 712/23 - Superscalar

Subclass of Class 712 - Electrical computers and digital processing systems: processing architectures and instruction processing (e.g., processors)
Definition: Subject matter comprising an architecture which determines
No. of patents: 990
Last issue date: 12/06/2011

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Number	Title	Issue Date
5367650	Method and apparauts for parallel exchange operation in a pipelined processor A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data regis...	11/22/1994
5367703	Method and system for enhanced branch history prediction accuracy in a superscalar processor system A method and system for enhanced branch history prediction accuracy in a superscalar processor system by maintaining branch history tables which include a separate branch history for each instruction fetch position within a multi-instruction access. In a ...	11/22/1994
5367694	RISC processor having a cross-bar switch An instruction cache unit output four instructions, each constituted by 32 bits, which are input to an instruction supplier. The instruction supplier distributes the four instructions to five. The five instructions are selectively supplied to two integer/...	11/22/1994
5363495	Data processing system with multiple execution units capable of executing instructions out of sequence A data processing system is provided that includes a plurality of execution units each including independent circuits for storing and executing instructions. A circuit is also included for providing instructions from a sequence of instructions to the exec...	11/08/1994
5359718	Early scalable instruction set machine alu status prediction apparatus An apparatus implementing an algorithm for generating carries due to the second instruction of an interlocked instruction pair when executing all combinations of logical as well as arithmetic instruction pairs is developed. The algorithm is then applied t...	10/25/1994
5357617	Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor A hybrid pipelined processor and associated processing methods are described for separately handling substantially concurrently in a time division manner multiple program instruction threads. The hybrid architecture includes an instruction fetch unit, an ...	10/18/1994
5349692	Instruction handling sequence control system for simultaneous execution of vector instructions An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or write...	09/20/1994
5337415	Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilizat...	08/09/1994
5333281	Advanced instruction execution system for assigning different indexes to instructions capable of parallel execution and same indexes to instructions incapable of parallel execution In an instruction processing unit of an information processing system in which operable instructions are executed as executing instructions on operands held by operand registers to store results of execution in result registers and in which a bypass arran...	07/26/1994
5303356	System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in t...	04/12/1994
5301341	Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions A mechanism is presented for detecting overflow in an interlock collapsing hardware apparatus that simultaneously executes two instructions. The overflow is determined as if the second instruction executes by itself using results from execution of the fir...	04/05/1994
5299319	High performance interlock collapsing SCISM ALU apparatus Three high performance implementations for an interlock collapsing ALU are presented as alternative embodiments. The critical path delay of each embodiment provides reduction in delay. For one of the implementations the delay is shown to be an equivalent ...	03/29/1994
5293500	Parallel processing method and apparatus A parallel processor is provided with a plurality of independently operable command units and a plurality of function units each connected to the command unit. A data unit, a register file, and a carry bit are shared such that the command and function uni...	03/08/1994
5291615	Instruction pipeline microprocessor An instruction pipeline type microprocessor comprises an operation execution section consisting of a first operation execution section for executing instructions having no memory operand, a second operation execution section for executing instructions hav...	03/01/1994
5278986	System and method for compiling a source code supporting data parallel variables A compiler for compiling a computer program which is adapted for use with a data parallel computer. The compiler supports variables which involve parallelism. Variables which involve parallelism are parallel variables, templates for parallel variables cal...	01/11/1994
5233694	Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers i...	08/03/1993
5226166	Parallel operation processor with second command unit A parallel processor is provided with a plurality of independently operable command units and a plurality of function units each connected to the command unit. In order to operate the command and functions units in parallel without any conflict, a data un...	07/06/1993
5214763	Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer sys...	05/25/1993
5212773	Wormhole communications arrangement for massively parallel processor A parallel processor array is disclosed comprising an array of processor/memories and devices for interconnecting these processor/memories in an n-dimensional pattern having at least 2n nodes through which data may be routed from any processor/...	05/18/1993
5202967	Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder is decoding an instruction, the probabili...	04/13/1993
5197135	Memory management for scalable compound instruction set machines with in-memory compounding A digital computer system is described which is capable of processing 2 or more computer instructions in parallel and which has the capability of generating compounding tag information for those instructions, the compounding tag information being associat...	03/23/1993
5197130	Cluster architecture for a highly parallel scalar/vector multiprocessor system A cluster architecture for a highly parallel multiprocessor computer processing system is comprised of one or more clusters of tightly-coupled, high-speed processors capable of both vector and scalar parallel processing that can symmetrically access share...	03/23/1993
5185872	System for executing different cycle instructions by selectively bypassing scoreboard register and canceling the execution of conditionally issued instruction if needed resources are busy A scbok line is connected to a register file and other units, such as an execution unit and a multiply/divide unit, in a data processing system. A mem scbok line is connected to the register file and other units, such as an instruction unit and a memory i...	02/09/1993
5136697	System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to in...	08/04/1992
5133077	Data processor having multiple execution units for processing plural classs of instructions in parallel A data processor is disclosed which enables the selective simultaneous or asynchronous execution of mutually independent instructions of different classes in parallel coupled execution units and which enables the sequential execution of mutually dependent...	07/21/1992
5075840	Tightly coupled multiprocessor instruction synchronization A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An in...	12/24/1991
4766566	Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing Performance of a VLSI processor of the reduced instruction set computer (RISC) type is enhanced by executing two instructions simultaneously in the two execution units of the processor. There is very little increase in the cost of hardware. Three embodime...	08/23/1988
4752873	Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution In accordance with the invention, there are disposed a logical register group and a physical register group. Direct access is made to the logical register group on the basis of a register number designated by an instruction. To make access to the physical...	06/21/1988
4521851	Central processor A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit exe...	06/04/1985
4199811	Microprogrammable computer utilizing concurrently operating processors A microprogrammable CPU for a computer utilizes an architecture wherein macro instructions of the computer repertoire are executed by micro instruction routines stored in a control store memory. The micro instruction routines are comprised of micro instru...	04/22/1980

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Class 712/23 - Superscalar