Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 7328330 | Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processor A method, an apparatus and a computer program product are provided for the managing of SIMD instructions and GP instructions within an instruction pipeline of a processor. The SIMD instructions and the GP instructions share the same “front-end” pipelines within ... | 02/05/2008 |
| 7324106 | Translation of register-combiner state into shader microcode An apparatus and method for translating fixed function state into a shader program. Fixed function state is received and stored and when a new shader program is detected the fixed function state is translated into shader program instructions. Registers specified by ... | 01/29/2008 |
| 7325124 | System and method of execution of register pointer instructions ahead of instruction issue A pipeline system and method includes a plurality of operational stages. The stages include a pointer register stage which stores pointer information and updates, and a rename and dependence checking stage located downstream of the pointer register stage, which rena... | 01/29/2008 |
| 7318145 | Random slip generator A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the sys... | 01/08/2008 |
| 7315934 | Data processor and program for processing a data matrix A data processor has sixteen processing elements that each include a register file and an arithmetic logic unit. A network unit connects between the register files of the processing elements and the arithmetic logic units of the processing elements. The network unit... | 01/01/2008 |
| 7313676 | Register renaming for dynamic multi-threading A register renaming technique for dynamic multithreading. One disclosed embodiment includes a register map to store up to M×N values to map M registers for N threads. A set of N values, one per thread, and a set of state bits is associated with each of the M regist... | 12/25/2007 |
| 7310723 | Methods and systems employing a flag for deferring exception handling to a commit or rollback point Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is to be deferred. An exception corresponding to the event is generated if... | 12/18/2007 |
| 7308559 | Digital signal processor with cascaded SIMD organization A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for s... | 12/11/2007 |
| 7301792 | Apparatus and method of ordering state transition rules for memory efficient, programmable, pattern matching finite state machine hardware A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory su... | 11/27/2007 |
| 7302690 | Method and apparatus for transparently sharing an exception vector between firmware and an operating system A method, apparatus and computer instructions for handling exception vectors by firmware. An exception vector is identified to form an identified exception vector when control is passed from an operating system to the firmware. The identified exception vector is sav... | 11/27/2007 |
| 7302556 | Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are received for a set of constraints for generating test simulation vect... | 11/27/2007 |
| 7293161 | Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for exe... | 11/06/2007 |
| 7293162 | Split data-flow scheduling mechanism A scheduling scheme and mechanism for a processor system is disclosed. The scheduling scheme provides a reservation station system that includes a control reservation station and a data reservation station. The reservation station system receives an operational entr... | 11/06/2007 |
| 7290253 | Prediction mechanism for subroutine returns in binary translation sub-systems of computers A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the retur... | 10/30/2007 |
| 7290261 | Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processor A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The... | 10/30/2007 |
| 7287152 | Conditional execution per lane A computer system for conditionally performing an operation defined in a computer instruction, an execution unit of the computer system comprises at least one operand store for holding operands on which an operation defined in an instruction is to be performed, wher... | 10/23/2007 |
| 7287151 | Communication path to each part of distributed register file from functional units in addition to partial communication network A VLIW processor comprising a plurality of functional units (1, 3, 5, 7), a distributed register file (9, 11, 13, 15) accessible by the functional units (1, 3, 5, 7), a partially connected communication network (17) for coupling the funct... | 10/23/2007 |
| 7284117 | Processor that predicts floating point instruction latency based on predicted precision A processor includes a prediction circuit and a floating point unit. The prediction circuit is configured to predict an execution latency of a floating point operation. The floating point unit is coupled to receive the floating point operation for execution, and is ... | 10/16/2007 |
| 7281119 | Selective vertical and horizontal dependency resolution via split-bit propagation in a mixed-architecture system having superscalar and VLIW modes A computer system supplies instructions simultaneously to a plurality of parallel execution pipelines in either superscalar mode or very long instruction word mode with checks for vertical and horizontal dependency between instructions, the horizontal dependency che... | 10/09/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7281120 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an inter... | 10/09/2007 |
| 7278011 | Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store... | 10/02/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7272748 | Method and apparatus to detect and recover from a stack frame corruption A prologue and an epilogue of a function are hooked. Completion of the prologue is stalled in a first state of a stack frame, and a copy of the first state of the stack frame is saved. Completion of the prologue is initiated, permitting execution of the function. Co... | 09/18/2007 |
| 7269715 | Instruction grouping history on fetch-side dispatch group formation An improved method, apparatus, and computer instructions for grouping instructions processed in equal sized sets. A current set of instructions is received in an instruction cache for dispatching. A determination is made as to whether any instructions in the current... | 09/11/2007 |
| 7269716 | Processor to efficiently rename decoded condition codes and instruction control method thereof A following CC read instruction which is decoded simultaneously with a previous CC update instruction is developed into a multiflow. The first flow is set to a no-operation. A CC renaming update is executed by a CC renaming map update processing unit by the decoding... | 09/11/2007 |
| 7266811 | Methods, systems, and computer program products for translating machine code associated with a first processor for execution on a second processor Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated progra... | 09/04/2007 |
| 7266675 | Processor including a register file and method for computing flush masks in a multi-threaded processing system A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implement... | 09/04/2007 |
| 7263601 | Sequencer unit with instruction buffering A sequencer unit includes a first instruction processing unit, an instruction buffer and a second instruction processing unit. The first instruction processing unit is adapted for receiving and processing a stream of instructions, and for issuing, in case data is re... | 08/28/2007 |
| 7263624 | Methods and apparatus for power control in a scalable array of processor elements Low power architecture features and techniques are provided in a scalable array indirect VLIW processor. These features and techniques include power control of a reconfigurable register file, conditional power control of multi-cycle operations and indirect VLIW util... | 08/28/2007 |
| 7260702 | Systems and methods for running a legacy 32-bit x86 virtual machine on a 64-bit x86 processor The present invention provides a virtualized computing systems and methods for transitioning in real time between LONG SUPER-MODE and LEGACY SUPER-MODE in the x86-64 architecture. In doing so, a virtual machine, which relies on the traditional 32-bit modes, i.e., RE... | 08/21/2007 |
| 7260217 | Speculative execution for data ciphering operations In one embodiment, a computer-implemented method comprises receiving a data cipher operation. The method also comprises processing the data cipher operation. The processing of the operation includes generating a number of portions of ciphertext from plaintext, where... | 08/21/2007 |
| 7257665 | Branch-aware FIFO for interprocessor data sharing A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to... | 08/14/2007 |
| 7254693 | Selectively prohibiting speculative execution of conditional branch type based on instruction bit A method, apparatus, and computer program product are disclosed for selectively prohibiting speculative conditional branch execution. A particular type of conditional branch instruction is selected. An indication is stored within each instruction that is the particu... | 08/07/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7249243 | Control word prediction and varying recovery upon comparing actual to set of stored words Techniques for control word prediction and speculative execution. In one embodiment, an apparatus includes a control word predictor, execution resources, and a comparison module. The control word predictor of this embodiment predicts a predicted control word for exe... | 07/24/2007 |
| 7246218 | Systems for increasing register addressing space in instruction-width limited processors A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommod... | 07/17/2007 |
| 7246220 | Architecture for hardware-assisted context switching between register groups dedicated to time-critical or non-time critical tasks without saving state In one embodiment of the present invention, a processing system for processing information efficiently and cost-effectively by switching between execution of time-critical and non-time-critical tasks includes a processing unit. The processing system further includes... | 07/17/2007 |
| 7243350 | Speculative execution for java hardware accelerator Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process bytecodes while waiting for the CPU to return a condition control variable. ... | 07/10/2007 |
| 7243214 | Stall optimization for an in-order, multi-stage processor pipeline which analyzes current and next instructions to determine if a stall is necessary According to some embodiments, a method determining a number of stages associated with an instruction to be executed via a processor pipeline, determining a number of stages associated with a subsequent instruction, and stalling the pipeline based on the number of s... | 07/10/2007 |
