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| Number | Title | Issue Date |
| 6477562 | Prioritized instruction scheduling for multi-streaming processors A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The priority codes determine in some embodiments relative access t... | 11/05/2002 |
| 6463525 | Merging single precision floating point operands Where it is desired to perform a double precision operation using single precision operands, first and second single precision operands are loaded into first and second respective rows of a re-order buffer, and third and fourth single precision operands a... | 10/08/2002 |
| 6453344 | Multiprocessor servers with controlled numbered of CPUs A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the total number of available CPUs. Software licensing costs ... | 09/17/2002 |
| 6442670 | Data processing system including a shared memory resource circuit A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a ... | 08/27/2002 |
| 6438680 | Microprocessor When a decision circuit (217) incorporated in a control circuit (21) in an instruction decode unit (2) in a microprocessor (1) decides that an integer operation unit (4) can not execute a following sub instruction, the decision circuit (217) controls each... | 08/20/2002 |
| 6438677 | Dynamic handling of object versions to support space and time dimensional program execution One embodiment of the present invention provides a system that supports space and time dimensional program execution by facilitating accesses to different versions of a memory element. The system supports a head thread that executes program instructions a... | 08/20/2002 |
| 6434689 | Data processing unit with interface for sharing registers by a processor and a coprocessor An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least ... | 08/13/2002 |
| 6434693 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose mai... | 08/13/2002 |
| 6427201 | Information processing apparatus for entertainment system utilizing DMA-controlled high-speed transfer and processing of routine data Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a main CPU 20 has a CPU core 21, having a parallel computational mechanism, a command cache 22 an... | 07/30/2002 |
| 6415354 | Pipelined methods and apparatus for weight selection and content addressable memory searches When a search key is supplied to a content addressable memory (CAM), the CAM signals indicate which CAM entries have matched the key. These signals are provided to a weight array to select the entry of the highest priority. Each entry's priority is indica... | 07/02/2002 |
| 6412062 | Injection control mechanism for external events The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match betw... | 06/25/2002 |
| 6412061 | Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be executed is received and a number of stages of the pipeline ... | 06/25/2002 |
| 6408375 | System and method for register renaming A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable ad... | 06/18/2002 |
| 6408377 | Dynamic allocation of resources in multiple microprocessor pipelines A microprocessor having M parallel pipelines and N arithmetic logic units, where N is less than M. A single instruction fetch stage fetches multi-stage instructions, and a single instruction decoder provides a parallel set of three instructions to the thr... | 06/18/2002 |
| 6405304 | Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list A technique for managing register assignments. The technique involves maintaining, in a register list memory circuit having entries that respectively correspond to physical registers, a list of register assignments that assign logical registers to the phy... | 06/11/2002 |
| 6397319 | Process for executing highly efficient VLIW A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code "cc" that indicates a branch operation which uses a ... | 05/28/2002 |
| 6385719 | Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the b... | 05/07/2002 |
| 6385715 | Multi-threading for a processor utilizing a replay queue A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining w... | 05/07/2002 |
| 6381689 | Line-oriented reorder buffer configured to selectively store a memory operation result in one of the plurality of reorder buffer storage locations corresponding to the executed instruction A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated wh... | 04/30/2002 |
| 6378060 | System to implement a cross-bar switch of a broadband processor The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in response to partially-decoded instruction information and in resp... | 04/23/2002 |
| 6360309 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containi... | 03/19/2002 |
| 6353881 | Supporting space-time dimensional program execution by selectively versioning memory updates A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculativ... | 03/05/2002 |
| 6351804 | Control bit vector storage for a microprocessor A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The control bits are divided into multiple control vectors, each ve... | 02/26/2002 |
| 6349382 | System for store forwarding assigning load and store instructions to groups and reorder queues to keep track of program order In a load/store unit within a microprocessor, load and store instructions are executed out of order. The load and store instructions are assigned tags in a predetermined manner, and then assigned to load and store reorder queues for keeping track of the p... | 02/19/2002 |
| 6343359 | Result forwarding cache An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics--complexity, power, and timing--that are not significantly impacted by the number of stages in the microproce... | 01/29/2002 |
| 6341343 | Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUs Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operan... | 01/22/2002 |
| 6341347 | Thread switch logic in a multiple-thread processor A processor includes a thread switching control logic that performs a fast thread-switching operation in response to an L1 cache miss stall. The fast thread-switching operation implements one or more of several thread-switching methods. A first thread-swi... | 01/22/2002 |
| 6339822 | Using padded instructions in a block-oriented cache A microprocessor configured to cache basic blocks of instructions is disclosed. The microprocessor may comprise decoding logic, a basic block cache, and a branch prediction unit. The decoding logic is coupled to receive and decode variable-length instruct... | 01/15/2002 |
| 6336178 | RISC86 instruction set An internal RISC-type instruction structure furnishes a fixed bit-length template including a plurality of defined bit fields for a plurality of operation (Op) formats. One format includes an instruction-type bit field, two source-operand bit fields and o... | 01/01/2002 |
| 6336160 | Method and system for dividing a computer processor register into sectors and storing frequently used values therein A method and system for dividing computer processor registers into sectors and storing frequently used data in the most significant unused sectors. The method includes sector renaming that is performed on each individual sector (i.e., on a sector-by-secto... | 01/01/2002 |
| 6336182 | System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system... | 01/01/2002 |
| 6332187 | Cumulative lookahead to eliminate chained dependencies A processor is configured to generate lookahead values using a cumulative constant. The processor classifies operations to a particular register (e.g. the stack pointer register, or ESP in an embodiment employing the x86 instruction set architecture) as e... | 12/18/2001 |
| 6330660 | Method and apparatus for saturated multiplication and accumulation in an application specific signal processor An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory,... | 12/11/2001 |
| 6330657 | Pairing of micro instructions in the instruction queue An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then th... | 12/11/2001 |
| 6330661 | Reducing inherited logical to physical register mapping information between tasks in multithread system using register group identifier A register content inheriting system contributes for realization of register content inheriting with a hardware of simple construction in a multithread multi-processor. Respective thread execution units and physical common register are provided. Using a r... | 12/11/2001 |
| 6324639 | Instruction converting apparatus using parallel execution code A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction... | 11/27/2001 |
| 6313766 | Method and apparatus for accelerating software decode of variable length encoded information A method and apparatus to accelerate variable length decode is disclosed. The system includes a logic device to receive a bit stream of variable length encoded information. The logic device outputs a fixed length value corresponding to a variable length c... | 11/06/2001 |
| 6311261 | Apparatus and method for improving superscalar processors The invention involves new microarchitecture apparatus and methods for superscalar microprocessors that support multi-instruction issue, decoupled dataflow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and preci... | 10/30/2001 |
| 6308259 | Instruction queue evaluating dependency vector in portions during different clock phases An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to dete... | 10/23/2001 |
| 6304953 | Computer processor with instruction-specific schedulers One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the first scheduler and adapted to dispatch a second type of compu... | 10/16/2001 |
