Bizarre Patents
Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8074052 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions embodied in software on a tangible computer-readable storage medium. A source supplies instructions to be executed by a functional unit. A queue having a plurality of slots containing tags which are used for... | 12/06/2011 |
| 7941636 | RISC microprocessor architecture implementing multiple typed register sets Disclosed herein is an apparatus that implements multiple typed register sets, and applications thereof. The apparatus includes an execution unit and a register file. The execution unit is configured to execute instructions including one or more fields. The register... | 05/10/2011 |
| 7941635 | High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a paral... | 05/10/2011 |
| 7844797 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 11/30/2010 |
| 7802074 | Superscalar RISC instruction scheduling A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accesse... | 09/21/2010 |
| 7739482 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 06/15/2010 |
| 7734897 | Allocation of memory access operations to memory access capable pipelines in a superscalar data processing apparatus and method having a plurality of execution threads A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operati... | 06/08/2010 |
| 7685402 | RISC microprocessor architecture implementing multiple typed register sets A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An int... | 03/23/2010 |
| 7555632 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a paral... | 06/30/2009 |
| 7555631 | RISC microprocessor architecture implementing multiple typed register sets A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An int... | 06/30/2009 |
| 7430651 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags whi... | 09/30/2008 |
| 7409670 | Scheduling logic on a programmable device implemented using a high-level language Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acce... | 08/05/2008 |
| 7401328 | Software-implemented grouping techniques for use in a superscalar data processing system A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature annotated thereto. An instruction prefetch unit of the processor fetches ... | 07/15/2008 |
| 7398375 | Technique for reduced-tag dynamic scheduling and reduced-tag prediction The present invention provides a dynamic scheduling scheme that uses reservation stations having at least one station that stores an at least two operand instruction. An allocator portion determines that the instruction, entering the pipeline, has one ready operand ... | 07/08/2008 |
| 7392369 | Decomposing architectural operation into speculative and architectural micro-operations for speculative execution of others and for violation check Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may ... | 06/24/2008 |
| 7376812 | Vector co-processor for configurable and extensible processor architecture A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/20/2008 |
| 7373481 | Distributed-structure-based parallel module structure and parallel processing method A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences con... | 05/13/2008 |
| 7373486 | Partially decoded register renamer In one embodiment, a renamer comprises a plurality of storage locations and compare circuitry. Each storage location is assigned to a respective renameable resource and is configured to store an identifier corresponding to a youngest instruction operation that write... | 05/13/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7370179 | Microprocessor The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of compo... | 05/06/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7366879 | Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor.... | 04/29/2008 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic sp... | 04/29/2008 |
| 7360221 | Task swap out in a multithreaded environment A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads execu... | 04/15/2008 |
| 7356674 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fe... | 04/08/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7353368 | Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, p... | 04/01/2008 |
| 7350056 | Method and apparatus for issuing instructions from an issue queue in an information handling system An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue inc... | 03/25/2008 |
| 7343478 | Register window system and method that stores the next register window in a temporary buffer The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching ... | 03/11/2008 |
| 7343595 | Method, apparatus and computer program for executing a program by incorporating threads There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined ... | 03/11/2008 |
| 7343473 | System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The s... | 03/11/2008 |
| 7343602 | Software controlled pre-execution in a multithreaded processor A processor capable of running multiple threads runs a program in one thread (called the “main” thread) and at least a portion of the same program in another thread (called the “pre-execution” thread). The program in the main thread includes instructions tha... | 03/11/2008 |
| 7339592 | Simulating multiported memories using lower port count memories An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multipl... | 03/04/2008 |
| 7340590 | Handling register dependencies between instructions specifying different width registers The present application describes a method and a processor for handling register dependency conflicts between lesser and greater width instructions, colloquially referred to as “evil twins.” If there is a register dependency between a greater width producer inst... | 03/04/2008 |
| 7340643 | Replay mechanism for correcting soft errors A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instruc... | 03/04/2008 |
| 7340692 | System LSI development apparatus and the method thereof for developing a system optimal to an application In this disclosure, based on change item definition information concerning system LSI development and design, software used for development and design of a system LSI that contains a processor having optional instructions defined therein is operated, and system LSI ... | 03/04/2008 |
| 7337307 | Exception handling with inserted status check command accommodating floating point instruction forward move across branch A process which automatically inserts commands that test for and raise exceptions indicating floating point status exceptions into a sequence of instructions to be executed, re-ordering a pipelined instructions by moving a floating point instruction from after a bra... | 02/26/2008 |
| 7330963 | Resolving all previous potentially excepting architectural operations before issuing store architectural operation Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may ... | 02/12/2008 |
