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| Number | Title | Issue Date |
| 8185723 | Method and apparatus to extract integer and fractional components from floating-point data A method is presented including decomposing a first value into many parts. Decomposing includes shifting (310) a rounded integer portion of the first value to generate a second value. Generating (320) a third value. Extracting (330) a plurality ... | 05/22/2012 |
| RE43145 | Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation ins... | 01/24/2012 |
| 8041927 | Processor apparatus and method of processing multiple data by single instructions A processor (and method) of processing multiple data by a single instruction includes first and second register sets each of which includes a plurality of registers, and an arithmetic unit to rearrange data being registered in the first and second register sets acco... | 10/18/2011 |
| 7987344 | Multithreaded programmable processor and system with partitioned operations A programmable processor and method for improving the performance of processors by incorporating an execution unit configurable to execute a plurality of instruction streams from the plurality of threads, wherein each instruction stream includes a group instruction ... | 07/26/2011 |
| 7971037 | Data processing device A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective da... | 06/28/2011 |
| 7962729 | Dynamic runtime range checking of different types on a register using upper and lower bound value registers for the register Software defects (e.g., array access out of bounds, stack overflow, infinite loops, and data corruption) occur due to integer values falling outside their expected range. Because programming languages do not include range-checking instructions as part of their langu... | 06/14/2011 |
| 7941650 | Microprocessor based on event-processing instruction set and event-processing method using the same Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set ... | 05/10/2011 |
| 7937568 | Adaptive execution cycle control method for enhanced instruction throughput A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular t... | 05/03/2011 |
| 7917737 | System and method for managing data A method of performing data and pointer compression includes, in a buffer which is formed between a processor and a level one cache and stores plural tags and full-word values associated with the tags, when the buffer is presented with an address, breaking the addre... | 03/29/2011 |
| 7904698 | Electronic parallel processing circuit for performing jump instructions The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and differe... | 03/08/2011 |
| 7877581 | Networked processor for a pipeline architecture A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stag... | 01/25/2011 |
| 7873815 | Digital signal processors with configurable dual-MAC and dual-ALU DSP architectures having improved performance are described. In an exemplary architecture, a DSP includes two MAC units and two ALUs, where one of the ALUs replaces an adder for one of the two MAC units. This DSP may be configured to operate in a dual-MAC/single-ALU... | 01/18/2011 |
| 7849294 | Sharing data in internal and memory representations with dynamic data-driven conversion Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determinatio... | 12/07/2010 |
| 7809931 | Arrangement, system and method for vector permutation in single-instruction multiple-data mircoprocessors A vector permutation system (100) for a single-instruction multiple-data microprocessor has a set of vector registers (110) which feed vectors to permutation logic (120) and then to a negate block (130) where they are permuted and selecti... | 10/05/2010 |
| 7797516 | Microcontroller with low-cost digital signal processing extensions A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions. ... | 09/14/2010 |
| 7783864 | Vertical and horizontal pipelining in a system for performing modular multiplication The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of s... | 08/24/2010 |
| 7779237 | Adaptive execution frequency control method for enhanced instruction throughput A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are sc... | 08/17/2010 |
| 7761693 | Data processing apparatus and method for performing arithmetic operations in SIMD data processing A data processing apparatus includes a register data store that stores data elements, an instruction decoder that decodes an “arithmetic returning high half” instruction, and a data processor that performs data processing operations controlled by the instruction... | 07/20/2010 |
| 7761694 | Execution unit for performing shuffle and other operations In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controll... | 07/20/2010 |
| 7694112 | Multiplexing output from second execution unit add/saturation processing portion of wider width intermediate result of first primitive execution unit for compound computation A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit in... | 04/06/2010 |
| 7590828 | Processing a data word in a plurality of processing cycles The invention relates to a processing of a data word in a plurality of processing cycles. In order to improve the efficiency of the processing, the data word is divided for each cycle into a plurality of successive data blocks. The blocks are shifted by one block fr... | 09/15/2009 |
| 7587582 | Method and apparatus for parallel arithmetic operations A method and apparatus for efficiently performing graphic operations are provided. This is accomplished by providing a processor that supports any combination of the following instructions: parallel multiply-add, conditional pick, parallel averaging, parallel power,... | 09/08/2009 |
| 7555635 | Data processing device A data processing device has an instruction decoder (1), a control logic unit (3), and ALU (4). The instruction decoder (1) decodes instruction codes of an arithmetic instruction. The control logic unit (3) detects the effective da... | 06/30/2009 |
| 7533249 | Reconfigurable integrated circuit, circuit reconfiguration method and circuit reconfiguration apparatus In order to reuse configuration information in a dynamic reconfiguration arithmetic circuit, data lines, address lines, a mask register and the like are required as hardware resources for rewriting only configuration information of dynamic reconfiguration arithmetic... | 05/12/2009 |
| 7496736 | Method of efficient digital processing of multi-dimensional data An innovative approach for constructing optimum, high-performance, efficient DSP systems may include a system organization to match compute execution and data availability rate and to organize DSP operations as loop iterations such that there is maximal reuse of dat... | 02/24/2009 |
| 7475229 | Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables,... | 01/06/2009 |
| 7457940 | System and method for managing data A system and method for managing data includes executing a set of instructions which are used for operating on compressed data and another set of instructions (e.g., different instructions) which are used for operating on uncompressed data. ... | 11/25/2008 |
| 7441106 | Distributed processing in a multiple processing unit environment Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is... | 10/21/2008 |
| 7434898 | Computer system, computer program, and addition method A computer system that makes it difficult to analyze the content of a calculation. In the computer system, a power operation unit performs the following operations using the input data “a” and “b”: ga=ga mod n, gb=gb | 10/14/2008 |
| 7434034 | SIMD processor executing min/max instructions The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30,... | 10/07/2008 |
| 7430656 | System and method of converting data formats and communicating between execution units A method and system including transmitting data in an architectural format between execution units in a multi-type instruction set architecture and converting data received in the architectural format to an internal format and data output in the internal format to t... | 09/30/2008 |
| 7424594 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations... | 09/09/2008 |
| 7409528 | Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third memory devices, which are connected with the first communication port... | 08/05/2008 |
| 7395302 | Method and apparatus for performing horizontal addition and subtraction A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs... | 07/01/2008 |
| 7392368 | Cross multiply and add instruction and multiply and subtract instruction SIMD execution on real and imaginary components of a plurality of complex data elements Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex d... | 06/24/2008 |
| 7392275 | Method and apparatus for performing efficient transformations with horizontal addition and subtraction A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs... | 06/24/2008 |
| 7389406 | Apparatus and methods for utilization of splittable execution units of a processor A partial execution unit of a splittable execution unit performs an operation on a portion of one or more arguments of a micro-operation to generate a first partial execution result of the micro-operation. A complementary portion of one of the arguments is passed th... | 06/17/2008 |
| 7373490 | Emptying packed data state during execution of packed data instructions A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instr... | 05/13/2008 |
| 7366882 | Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle. ... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
