Quotables
"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 8190861 | Micro-sequence based security model A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, e... | 05/29/2012 |
| 8190862 | Hardware device for processing the tasks of an algorithm in parallel A hardware device for processing the tasks of an algorithm of the type having a number of processes the execution of some of which depend on binary decisions has a plurality of task units (10, 12, 14), each of which are associated with a task defined as being... | 05/29/2012 |
| 8181002 | Merging checkpoints in an execute-ahead processor One embodiment of the present invention provides a system that merges checkpoints on a processor. The system starts by executing instructions speculatively during a speculative-execution episode. The system then generates a first checkpoint and a second checkpoint d... | 05/15/2012 |
| 8176300 | Method and apparatus for content based searching The scheduling of multiple request to be processed by a number of deterministic finite automata-based graph thread engine (DTE) workstations is processed by a novel scheduler. The scheduler may select an entry from an instruction in a content search apparatus. Using... | 05/08/2012 |
| 8171265 | Accelerating traceback on a signal processor A method executed by an instruction set on a processor is described. The method includes providing a tbbit instruction, inputting a first index for the tbbit instruction, loading a second value for the tbbit instruction, wherein the second value comprises at least 2... | 05/01/2012 |
| 8166282 | Multi-version register file for multithreading processors with live-in precomputation Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative multithreading. For at least one embodiment, live-in values for a speculative thread are computed via execution of ... | 04/24/2012 |
| 8166283 | Generator of a signal with an adjustable waveform A generator of a signal including a memory in which instructions are stored, each instruction including a code portion and an argument portion; circuitry for successively reading instructions stored in the memory; decoding circuitry capable of receiving, for each re... | 04/24/2012 |
| 8151093 | Software programmable hardware state machines The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. In example embodiments, processors, systems and methods are provided to prevent an unwanted change in arch... | 04/03/2012 |
| 8151094 | Dynamically estimating lifetime of a semiconductor device The present invention includes a method for obtaining dynamic operating parameter information of a semiconductor device such as a processor, determining dynamic usage of the device, either as a whole or for one or more portions thereof, based on the dynamic operatin... | 04/03/2012 |
| 8103857 | Microprocessor control apparatus as well as method and program for the same There is provided with a microprocessor control apparatus for controlling an operating speed of a microprocessor which executes a program including instruction codes, including: a state observing unit observing an execution state of the program at predetermined timi... | 01/24/2012 |
| 8099584 | Methods for scalably exploiting parallelism in a parallel processing system Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-prob... | 01/17/2012 |
| 8095780 | Register systems and methods for a multi-issue processor A multi-issue processor includes a register file and a plurality of issue slots, each one of the plurality of issue slots having a plurality of functional units and a plurality of holdable registers. The plurality of issue slots include a first set of issue slots an... | 01/10/2012 |
| 8095781 | Instruction fetch pipeline for superscalar digital signal processors and method of operation thereof A next program counter (PC) value generator. The next PC value generator includes a discontinuity decoder that is provide to detect a discontinuity instruction among a plurality of instructions and a tight loop decoder that is provide to: a) detect a tight loop inst... | 01/10/2012 |
| 8090932 | Communication bus with hidden pre-fetch registers A system-on-chip including a processor, a control module, a first plurality of data registers, a second plurality of data registers, a plurality of address registers, and a first control module. The first plurality of data registers are configured to store data. The... | 01/03/2012 |
| 8082424 | Determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation Methods, apparatus, and products are disclosed for determining when a set of compute nodes participating in a barrier operation on a parallel computer are ready to exit the barrier operation that includes, for each compute node in the set: initializing a barrier cou... | 12/20/2011 |
| 8074057 | Systems and methods for controlling instruction throughput Systems and methods for controlling instruction throughput are disclosed. One embodiment of a system may comprise a comparator that determines a difference value in an actual instructions per clock cycle throughput and a target instructions per clock cycle throughpu... | 12/06/2011 |
| 8069337 | Methods and apparatus for dynamic instruction controlled reconfigurable register file A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by eac... | 11/29/2011 |
| 8051276 | Operating system thread scheduling for optimal heat dissipation A method and system for thread scheduling for optimal heat dissipation are provided. Temperature sensors measure temperature throughout various parts of a processor chip. The temperatures detected are reported to an operating system or the like for scheduling thread... | 11/01/2011 |
| 8051277 | Programmable arithmetic logic unit cluster A Programmable Arithmetic Logic Unit Cluster is claimed. The plurality of Programmable Logic Blocks (50) in the cluster are in a physically linear sequence; but, will process data in parallel when the data pathways permit. A physically linear and operationall... | 11/01/2011 |
| 8046567 | Multi-threaded processor architecture A multi-threaded processor that is capable of responding to, and processing, multiple low-latency-tolerant events concurrently and while using relatively slow, low-power memories is disclosed. The illustrative embodiment comprises a multi-threaded processor, which i... | 10/25/2011 |
| 8041926 | Transparent concurrent atomic execution Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include applicatio... | 10/18/2011 |
| 8028152 | Hierarchical multi-threading processor for executing virtual threads in a time-multiplexed fashion A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instr... | 09/27/2011 |
| 8024551 | Pipelined digital signal processor Reducing pipeline stall between a compute unit and address unit in a processor can be accomplished by computing results in a compute unit in response to instructions of an algorithm; storing in a local random access memory array in a compute unit predetermined sets ... | 09/20/2011 |
| 8006073 | Simultaneous speculative threading light mode A system and method for management of resource allocation of threads for efficient execution of instructions. Prior to dispatching decoded instructions of a first thread from the instruction fetch unit to a buffer within a scheduler, logic within the instruction fet... | 08/23/2011 |
| 7996656 | Attaching and virtualizing reconfigurable logic units to a processor In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and w... | 08/09/2011 |
| 7996657 | Reconfigurable computing circuit A reconfigurable computing circuit for reducing the amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration re... | 08/09/2011 |
| 7979679 | System and method for selectively controlling operations in lanes in an execution unit of a computer A computer system is disclosed capable of conditionally carrying out an operation defined in a computer instruction. The computer instruction is implemented on so-called packed operands, that is operands containing a plurality of packed objects in respective lanes. ... | 07/12/2011 |
| 7979680 | Multi-threaded parallel processor methods and apparatus A processor system may implement multiple contexts on one or more processors having a local memory. Code and/or data for first and second contexts may be respectively stored simultaneously in first and second regions of a processor's local memory, storing code and/o... | 07/12/2011 |
| 7975129 | Selective hardware lock disabling Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a... | 07/05/2011 |
| 7971035 | Using temperature data for instruction thread direction A data processing system having a memory for storing instructions and several central processing units for executing instructions, each central processing unit includes an adaptive power supply which provides, among other data, temperature information. Circuitry is ... | 06/28/2011 |
| 7971036 | Methods and apparatus for attaching application specific functions within an array processor A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node scalable array processor. VSPN memory hardware ... | 06/28/2011 |
| 7962727 | Method and apparatus for decompression of block compressed data System and method for decompressing data. A compressed data stream including contiguous variable length blocks is received, each block including multiple contiguous variable length data fields and a tag portion that includes multiple contiguous tag fields correspond... | 06/14/2011 |
| 7962726 | Recycling long multi-operand instructions A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory u... | 06/14/2011 |
| 7962728 | Data processor The data processor executes an instruction having a direction for write to a reference register of other instruction flow and an instruction having a direction for reference register invalidation. The data processor is arranged as a data processor having typical fun... | 06/14/2011 |
| 7953962 | Multiprocessor system and control method thereof A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store d... | 05/31/2011 |
| 7953961 | Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder An instruction processing circuit for a processor includes a decoder circuit, a cache circuit, a sequencer circuit operable to select a next sequence of operations, and an operations fetch circuit operable to convey the next sequence of operations to an execution ci... | 05/31/2011 |
| 7941647 | Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeli... | 05/10/2011 |
| 7941646 | Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a ... | 05/10/2011 |
| 7941645 | Isochronous pipelined processor with deterministic control An isochronous processor includes a state register, a functional unit, a control module, and an activation unit. The state register includes an arm buffer and an active buffer. The functional unit performs a transformation operation on the data stream in response to... | 05/10/2011 |
| 7941649 | SIMD processor executing min/max instructions A SIMD processor responds to a single min/max instruction to find the minimum or maximum valued data unit in an array of data units. The determined minimum/maximum value and an associated index value thereto may be output. Alternatively, the value of a data unit in ... | 05/10/2011 |
