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| Number | Title | Issue Date |
| 8127112 | SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole... | 02/28/2012 |
| 8122227 | SIMD processor for performing data filtering and/or interpolation A data processing circuit contains an instruction execution circuit that has an instruction set that comprises a SIMD instruction. The instruction execution circuit comprises a plurality of arithmetic circuits, arranged to perform N respective identical operations i... | 02/21/2012 |
| 8112614 | Parallel data processing systems and methods using cooperative thread arrays with unique thread identifiers as an input to compute an identifier of a location in a shared memory Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID... | 02/07/2012 |
| 8108653 | Processor architectures for enhanced computational capability and low latency A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial com... | 01/31/2012 |
| 8082419 | Residual addition for video software techniques According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing ... | 12/20/2011 |
| 8078836 | Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bits In-lane vector shuffle operations are described. In one embodiment a shuffle instruction specifies a field of per-lane control bits, a source operand and a destination operand, these operands having corresponding lanes, each lane divided into corresponding portions ... | 12/13/2011 |
| 8069334 | Parallel histogram generation in SIMD processor by indexing LUTs with vector data element values The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where ... | 11/29/2011 |
| 8060726 | SIMD microprocessor, image processing apparatus including same, and image processing method used therein A SIMD microprocessor, which can be included in an image processing apparatus using an image processing method used therein, includes a global processor and multiple processor elements controlled by the global processor. Each single processor element of the multiple... | 11/15/2011 |
| 8024550 | SIMD processor with each processing element receiving buffered control signal from clocked register positioned in the middle of the group Disclosed is an SIMD-type microprocessor comprising a processor element group, plural processor elements with an operation part and a register file being arranged therein and a processor element control signal generator configured to output a processor element contr... | 09/20/2011 |
| 8024549 | Two-dimensional processor array of processing elements A data processor apparatus comprises a plurality of data receiving means each for receiving data from a data source; a computational element coupleable to each of said data receiving means for performing an operation on said data; and a controller for controlling th... | 09/20/2011 |
| 8001506 | SIMD image forming apparatus for minimizing wiring distance between registers and processing devices A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access registers arranged in stages for storing image data; and multiple data ... | 08/16/2011 |
| 7962718 | Methods for performing extended table lookups using SIMD vector permutation instructions that support out-of-range index values A permutation instruction generates vector elements for a destination register using identified source and destination registers. A plurality of partial table lookups corresponding to an extended table produces a plurality of intermediate results. At least one sourc... | 06/14/2011 |
| 7925861 | Plural SIMD arrays processing threads fetched in parallel and prioritized by thread manager sequentially transferring instructions to array controller for distribution A data processor comprises a plurality of processing elements arranged in a first plurality of single instruction multiple data (SIMD) processing arrays, and comprises a second plurality of controllers for transferring instructions to the processing arrays. Each con... | 04/12/2011 |
| 7917727 | Data processing architectures for packet handling using a SIMD array An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in t... | 03/29/2011 |
| 7908461 | Cellular engine for a data processing system A data processing system includes an associative memory device containing n-cells, each of the n-cells includes a processing circuit. A controller is utilized for issuing one of a plurality of instructions to the associative memory device, while a clock device is ut... | 03/15/2011 |
| 7890733 | Processor memory system A data processor comprises a plurality of processing elements (PEs), with memory local to at least one of the processing elements, and a data packet-switched network interconnecting the processing elements and the memory to enable any of the PEs to access the memory... | 02/15/2011 |
| 7873812 | Method and system for efficient matrix multiplication in a SIMD processor architecture The new system provides for efficient implementation of matrix multiplication in a SIMD processor. The new system provides ability to map any element of a source vector register to be paired with any element of a second source vector register for vector operations, ... | 01/18/2011 |
| 7861060 | Parallel data processing systems and methods using cooperative thread arrays and thread identifier values to determine processing behavior Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID... | 12/28/2010 |
| 7856543 | Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; ... | 12/21/2010 |
| 7818540 | Vector processing system A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one o... | 10/19/2010 |
| 7818541 | Data processing architectures A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; ... | 10/19/2010 |
| 7814297 | Algebraic single instruction multiple data processing A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic (140) has a plurality of functional units (142, 144, 146) configured to execute in p... | 10/12/2010 |
| 7788468 | Synchronization of threads in a cooperative thread array A “cooperative thread array,” or “CTA,” is a group of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique thread identifier assigned at thread launch time that cont... | 08/31/2010 |
| 7783862 | Method and apparatus for an inductive doubling architecture One embodiment of the present invention is a processor that processes inductive doubling SIMD instructions, which processor includes: an Instruction Fetch Unit that loads a SIMD instruction and applies it as input to a SIMD Instruction Decode Unit; wherein the SIMD ... | 08/24/2010 |
| 7725681 | Parallel processing array A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configure... | 05/25/2010 |
| 7644255 | Method and apparatus for enable/disable control of SIMD processor slices Methods and apparatus provide for disabling at least some data path processing circuits of a SIMD processing pipeline, in which the processing circuits are organized into a matrix of slices and stages, in response to one or more enable flags during a given cycle. | 01/05/2010 |
| 7634637 | Execution of parallel groups of threads with per-instruction serialization In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads ... | 12/15/2009 |
| 7596679 | Interconnections in SIMD processor architectures A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 ... | 09/29/2009 |
| 7594095 | Multithreaded SIMD parallel processor with launching of groups of threads In a multithreaded processing core, groups of threads are launched in parallel for single-instruction, multiple-data (SIMD) execution by a set of parallel processing engines. Thread-specific input data for threads in a new SIMD group can be loaded directly into the ... | 09/22/2009 |
| 7584342 | Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID... | 09/01/2009 |
| 7539846 | SIMD processor with a subroutine control unit The invention relates to a method and an apparatus for controlling a digital signal processor having a number of arithmetic units (1a, 1b) which process a program (8). A control unit (5) is provided for independent control o... | 05/26/2009 |
| 7536532 | Merge operations of data arrays based on SIMD instructions A method and apparatus are provided to perform efficient merging operations of two or more streams of data by using SIMD instruction. Streams of data are merged together in parallel and with mitigated or removed conditional branching. The merge operations of the str... | 05/19/2009 |
| 7506135 | Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of histogram calculation by a factor of N times over a scalar processor where ... | 03/17/2009 |
| 7506136 | Parallel data processing apparatus A controller for controlling a data processor having a plurality of processor arrays, each of which includes a plurality of processing elements, comprises a retrieval unit operable to retrieve a plurality of incoming instructions streams in parallel with one another... | 03/17/2009 |
| 7454594 | Processor for realizing software pipelining with a SIMD arithmetic unit simultaneously processing each SIMD instruction on a plurality of discrete elements A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in par... | 11/18/2008 |
| 7447873 | Multithreaded SIMD parallel processor with loading of groups of threads In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to be processed received as a stream of input data blocks, and the inpu... | 11/04/2008 |
| 7444496 | Apparatus, system, and method for determining the consistency of a database An apparatus, system, and method are disclosed for determining the consistency of a database including indirect reference to data elements. There is provided an apparatus for determining consistency of a database. This database includes, in association with each dat... | 10/28/2008 |
| 7441099 | Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of ... | 10/21/2008 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7412587 | Parallel operation processor utilizing SIMD data transfers A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing eleme... | 08/12/2008 |
