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| Number | Title | Issue Date |
| 8131980 | Structure for dynamic livelock resolution with variable delay memory access queue A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within th... | 03/06/2012 |
| 8090931 | Microprocessor with fused store address/store data microinstruction A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register i... | 01/03/2012 |
| 8082423 | Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates A method and apparatus are provided for detecting and handling an instruction flush in a microprocessor system. A flush mechanism is provided that is distributed across all of the execution units in a data processing system. The flush mechanism does not require a ce... | 12/20/2011 |
| 8082422 | Pipelined processing The invention includes receiving a first instruction in an in-order execution processing pipeline; starting execution of the first instruction; determining a first set of internal operation bits indicating a prospective value of control bits upon complete execution ... | 12/20/2011 |
| 8078845 | Device and method for processing instructions based on masked register group size information A method and a device for processing instructions based on register group size information includes a pipelined processor, an instruction memory unit and a register file, whereas the pipelined processor includes a write-back unit and an execution unit. The device is... | 12/13/2011 |
| 8019974 | Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register A bypass circuit is provided in a pipeline processor. A pipeline register is provided between an instruction execution stage and a write-back stage. The pipeline register stores a data validity flag and a WRITE control flag to control writing data into a general pur... | 09/13/2011 |
| 8001362 | Processing unit A processing unit includes a plurality of thread execution units each provided with a performance analysis circuit for measuring various types of events resulting from execution of instructions and a commit stack entry unit for controlling the completion of executed... | 08/16/2011 |
| 7996655 | Multiport execution target delay queue FIFO array One embodiment provides a method of forwarding data in a processor. The method generally includes providing at least one cascaded delayed execution pipeline unit having at least a first pipeline and a second pipeline for executing first and second instructions in a ... | 08/09/2011 |
| 7987343 | Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) includin... | 07/26/2011 |
| 7984272 | Design structure for single hot forward interconnect scheme for delayed execution pipelines A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for forwarding data in a processor is provided. The design structure includes a processor. The processor includes at least one cascaded delayed exe... | 07/19/2011 |
| 7975128 | Apparatuses and programs for implementing a forwarding function The processor according to the present invention is a processor having a forwarding function and includes an attribute information holding unit (141) that holds attribute information regarding inhibition of writing to a register and a register write inhibitio... | 07/05/2011 |
| 7937566 | Processing bypass directory tracking system and method A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The configuration of the bits is utilized to det... | 05/03/2011 |
| 7921280 | Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirem... | 04/05/2011 |
| 7921279 | Operand and result forwarding between differently sized operands in a superscalar processor Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions com... | 04/05/2011 |
| 7822951 | System and method of load-store forwarding A system and method for data forwarding from a store instruction to a load instruction during out-of-order execution, when the load instruction address matches against multiple older uncommitted store addresses or if the forwarding fails during the first pass due to... | 10/26/2010 |
| 7774583 | Processing bypass register file system and method A processing bypass register file system and method are disclosed. In one embodiment a processing bypass register file includes a rotating head pointer, and a plurality of write ports, storage cells and read ports. The write ports receive processing result informati... | 08/10/2010 |
| 7774582 | Result bypassing to override a data hazard within a superscalar processor A data processing system including multiple execution pipelines each having multiple execution stages E1, E2, E3 may have instructions issued together in parallel despite a data dependency therebetween if it is detected that the result operand v... | 08/10/2010 |
| 7769987 | Single hot forward interconnect scheme for delayed execution pipelines A method and apparatus for forwarding data in a processor. The method includes providing at least one cascaded delayed execution pipeline unit having a first pipeline and a second pipeline, wherein the second pipeline executes instructions in a common issue group in... | 08/03/2010 |
| 7747841 | Method and apparatus for early load retirement in a processor system A technique known as checkpointed early load retirement, combines register checkpointing load-value prediction to manage long-latency loads. When a long-latency load reaches the retirement stage unresolved, the processor enters Clear mode by (1) taking a Checkpoint ... | 06/29/2010 |
| 7730285 | Data processing system with partial bypass reorder buffer and combined load/store arithmetic logic unit and processing method thereof A data processing system includes a plurality of functional units that selectively execute instructions. A register file includes a plurality of registers that store data corresponding to the instructions. A reorder buffer communicates with the register file and sto... | 06/01/2010 |
| 7730284 | Pipelined instruction processor with data bypassing and disabling circuit An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a firs... | 06/01/2010 |
| 7725687 | Register file bypass with optional results storage and separate predication register file in a VLIW processor This invention makes each register bypass forwarding register explicitly addressable in software. Software chooses whether to access the forwarding register immediately eliminating the need for complex automatic detection. Each instruction executes and always writes... | 05/25/2010 |
| 7725686 | Systems and methods for processing buffer data retirement conditions Systems and methods for determining whether to retire a data entry from a buffer using multiple retirement logic units. In one embodiment, each retirement unit concurrently evaluates retirement conditions for one of the buffer entries in an associated subset (e.g., ... | 05/25/2010 |
| 7698537 | Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instruction... | 04/13/2010 |
| 7673120 | Inter-cluster communication network and heirarchical register files for clustered VLIW processors A VLIW processor has a hierarchy of functional unit clusters that communicate through explicit control in the instruction stream and store data in register files at each level of the hierarchy. Explicit instructions transfer values between sub-clusters through a clu... | 03/02/2010 |
| 7640419 | Method for and a trailing store buffer for use in memory renaming Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient memory renaming. The method includes computing a store address, writing the store address in a first storage, writing data associated with the store addres... | 12/29/2009 |
| 7613906 | Advanced load value check enhancement Systems and methods for performing re-ordered computer instructions are disclosed. A computer processor loads a first value from a first memory address, and records both the first value and the second value in a table or queue. The processor stores a second value to... | 11/03/2009 |
| 7529913 | Late allocation of registers Embodiments of the present invention relate to a method and system for providing virtual identifiers corresponding to physical registers in a computer processor. According to the embodiments, the virtual identifiers may be used to represent the physical registers du... | 05/05/2009 |
| 7523296 | System and method for handling exceptions and branch mispredictions in a superscalar microprocessor An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out... | 04/21/2009 |
| 7519794 | High performance architecture for a writeback stage In one embodiment, the present invention includes an apparatus that has a plurality of buffers to store data resulting from operations of a processor pipeline, a pointer storage to store pointers, where each of the pointers is to point to one of the buffers, and one... | 04/14/2009 |
| 7506140 | Return data selector employing barrel-incrementer-based round-robin apparatus A return data selector is disclosed. A pipelined microprocessor includes N functional units that request to return data to the pipeline. In a given selection cycle, some of the functional units may not be requesting to return data. The return data selector includes ... | 03/17/2009 |
| 7500086 | Start transactional execution (STE) instruction to support transactional program execution One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program,... | 03/03/2009 |
| 7496735 | Method and apparatus for incremental commitment to architectural state in a microprocessor Method and hardware apparatus are disclosed for reducing the rollback penalty on exceptions in a microprocessor executing traces of scheduled instructions. Speculative state is committed to the architectural state of the microprocessor at a series of commit points w... | 02/24/2009 |
| 7484078 | Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering A data processing circuit contains a register file (17) with a write port and a pipeline of instruction processing stages (10a-d). A timing circuit (14) is arranged to time transfer of instruction dependent information between the ... | 01/27/2009 |
| 7475226 | System for managing data dependency using bit field instruction destination vector identifying destination for execution results A method of data processing includes fetching a sequence of instructions, assigning each instruction within the sequence a respective unique instruction tag, and associating a respective destination vector with each instruction. The destination vectors, which are of... | 01/06/2009 |
| 7475225 | Method and apparatus for microarchitecture partitioning of execution clusters Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution res... | 01/06/2009 |
| 7472258 | Dynamically shared group completion table between multiple threads An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instructio... | 12/30/2008 |
| 7444497 | Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using spe... | 10/28/2008 |
| 7426630 | Arbitration of window swap operations In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an i... | 09/16/2008 |
| 7424598 | Data processor The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machi... | 09/09/2008 |
