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| Number | Title | Issue Date |
| 8127116 | Dependency matrix with reduced area and power consumption A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes t... | 02/28/2012 |
| 7991980 | Concurrent execution of instructions in a processing system A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable pro... | 08/02/2011 |
| 7984271 | Processor device for out-of-order processing having reservation stations utilizing multiplexed arithmetic pipelines A processor device having a reservation station (RS) is concerned. In case the processor device has plural RS, the RS is associated with an arithmetic pipeline, and two RS make a pair. When one RS of the pair cannot dispatch an instruction to an associated arithmeti... | 07/19/2011 |
| 7979678 | System and method for register renaming A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instr... | 07/12/2011 |
| 7971034 | Reduced overhead address mode change management in a pipelined, recycling microprocessor A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction f... | 06/28/2011 |
| 7958337 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar ... | 06/07/2011 |
| 7958339 | Instruction execution control device and instruction execution control method An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. And the instruction execution control device has a thread selection circuit (30) which detects a state where an instruction has not been completed f... | 06/07/2011 |
| 7958338 | Instruction execution control device and instruction execution control method An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (22-0, 22-1) for each thread, and a selection circuit (32, 24) which, when an operand dat... | 06/07/2011 |
| 7949857 | Method and system for determining multiple unused registers in a processor An improved method, device and system are presented for selecting a predetermined number of unused registers in a processor. The method includes partitioning registers in a processor into subsets; searching each subset for an unused register; determining whether eve... | 05/24/2011 |
| 7934078 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out... | 04/26/2011 |
| 7925868 | Suppressing register renaming for conditional instructions predicted as not executed Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be ... | 04/12/2011 |
| 7904697 | Load register instruction short circuiting method An apparatus and method for executing a Load Register instruction in which the source data of the Load Register instruction is retained in its original physical register while the architected target register is mapped to this same physical target register. In this s... | 03/08/2011 |
| 7844800 | Method for renaming a large number of registers in a data processing system using a background channel A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and... | 11/30/2010 |
| 7840783 | System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths A system, method, and computer program product are provided for performing a register renaming operation utilizing hardware which operates in at least two modes. In operation, hardware is operated in at least two modes including a first mode for operating the hardwa... | 11/23/2010 |
| 7809930 | Selective suppression of register renaming A register renaming unit has mapping control circuitry which serves to suppress unnecessary mapping operations in dependence upon a detected current state of the data processing system. One example of circumstances which can be detected from the current state and in... | 10/05/2010 |
| 7769986 | Method and apparatus for register renaming A method and apparatus for register renaming are provides in the illustrative embodiments. A mapper receives a request for a data in a logical register. The mapper searches an in-flight map table and a set of architected map tables for the data in the logical regist... | 08/03/2010 |
| 7761691 | Method for allocating registers using simulated annealing controlled instruction scheduling A method for scheduling instructions for clustered digital signal processors comprising a plurality of clusters, each cluster including at least two functional units and a first register file having a first unit, a second unit and a single set of access ports shared... | 07/20/2010 |
| 7747840 | Method for latest producer tracking in an out-of-order processor, and applications thereof Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register st... | 06/29/2010 |
| 7721071 | System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor A processor core and a method for distributive scoreboard scheduling in an out-of-order processor pipeline are described herein. In an embodiment, control logic appends operand availability bits to each instruction. The appended operand availability bits form a dist... | 05/18/2010 |
| 7711929 | Method and system for tracking instruction dependency in an out-of-order processor A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An outpu... | 05/04/2010 |
| 7711928 | Method and structure for explicit software control using scoreboard status information A user is provided with means to sample memory hierarchy via software. This allows a user to enhance memory-level parallelism via software. A status of information needed for execution of a second computer program instruction is read in response to execution of a fi... | 05/04/2010 |
| 7669039 | Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename ... | 02/23/2010 |
| 7660971 | Method and system for dependency tracking and flush recovery for an out-of-order microprocessor A method for dependency tracking and flush recovery for an out-of-order processor includes recording, in a last definition (DEF) data structure, an identifier of a first instruction as the most recent instruction in an instruction sequence that defines contents of t... | 02/09/2010 |
| 7660970 | Register allocation method and system for program compiling Disclosed is a data processing system and method. The data processing method determines the number of static registers and the number of rotating registers for assigning a register to a variable contained in a certain program, assigns the register to the variable ba... | 02/09/2010 |
| 7631167 | System for SIMD-oriented management of register maps for map-based indirect register-file access A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of a... | 12/08/2009 |
| 7613905 | Partial register forwarding for CPUs with unequal delay functional units A data processing apparatus includes a register file and a plurality of functional units. At least one and not all the plurality of the functional units is a critical functional unit. Each critical functional unit supplies its output to a pipeline register. A compar... | 11/03/2009 |
| 7590827 | Processor and instruction control method having a storage of latest register for updating data of source operands, and instruction control A latest register update buffer which stores latest register update data is allocated and prepared every general register for storing source data. A latest register update processing unit stores a value in the general register as latest register update data into the... | 09/15/2009 |
| 7577825 | Method for data validity tracking to determine fast or slow mode processing at a reservation station Devices, systems, and methods may perform micro-operation processing with data validity tracking to determine fast or slow mode processing at a reservation station. A method includes determining whether a condition related to validity of data in a reorder buffer of ... | 08/18/2009 |
| 7571302 | Dynamic data dependence tracking and its application to branch prediction A data dependence table in RAM relates physical register addresses to instructions such that for each instruction, the registers on whose data the instruction depends are identified. The table is updated for each instruction added to the pipeline. For a branch instr... | 08/04/2009 |
| 7565511 | Working register file entries with instruction based lifetime A technique for operating a computing apparatus includes allocating a working register file entry corresponding to a register in a working register file when an instruction referencing the register proceeds through a particular stage of the computing apparatus. The ... | 07/21/2009 |
| 7558945 | System and method for register renaming A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instr... | 07/07/2009 |
| 7539850 | Enhanced virtual renaming scheme and deadlock prevention therefor In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously execu... | 05/26/2009 |
| 7516305 | System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out... | 04/07/2009 |
| 7506139 | Method and apparatus for register renaming using multiple physical register files and avoiding associative search A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to ... | 03/17/2009 |
| 7496734 | System and method for handling register dependency in a stack-based pipelined processor There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, wh... | 02/24/2009 |
| 7490226 | Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor A method and related apparatus is provided for a processor having a number of registers, wherein instructions are sequentially issued to move through a sequence of execution stages, from an initial stage to a final write back stage. As a method, an embodiment includ... | 02/10/2009 |
| 7487336 | Method for register allocation during instruction scheduling The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands. ... | 02/03/2009 |
| 7487337 | Back-end renaming in a continual flow processor pipeline Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of t... | 02/03/2009 |
| 7475224 | Register map unit supporting mapping of multiple register specifier classes Embodiments of this invention relate to sharing resources on a semiconductor between multiple functional units to reduce the number of register rename mappers and particularly to providing a way to share a CAM mapper between two distinct physical register files. In ... | 01/06/2009 |
| 7434032 | Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to... | 10/07/2008 |
