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| Number | Title | Issue Date |
| 6360309 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containi... | 03/19/2002 |
| 6360313 | Instruction cache associative crossbar switch A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes stora... | 03/19/2002 |
| 6353881 | Supporting space-time dimensional program execution by selectively versioning memory updates A system is provided that facilitates space and time dimensional execution of computer programs through selective versioning of memory elements located in a system heap. The system includes a head thread that executes program instructions and a speculativ... | 03/05/2002 |
| 6353880 | Four stage pipeline processing for a microcontroller A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, a... | 03/05/2002 |
| 6351802 | Method and apparatus for constructing a pre-scheduled instruction cache A method of scheduling instructions in a computer processor. The method comprises fetching instructions to create an in-order instruction buffer, and scheduling instruction from the instruction buffer into instruction slots within instruction vectors in a... | 02/26/2002 |
| 6351807 | Data processing system utilizing multiple resister loading for fast domain switching A processor (40) in a data processing system simultaneously loads multiple registers (60) with a single value for fast domain switching. A domain switch instruction asserts a register block write signal (112) along with the register write signal (116) whe... | 02/26/2002 |
| 6351806 | Risc processor using register codes for expanded instruction set A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain operation codes multiple meanings. For most operations, t... | 02/26/2002 |
| 6349381 | Pipelined instruction dispatch unit in a superscalar processor A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, ... | 02/19/2002 |
| 6345355 | Method and apparatus for distributing commands to a plurality of circuit blocks A command memory stores commands in memory words. Each command has a label field and an action field. The commands are consolidated to reduce the amount of information stored in the command memory. A control unit interprets the commands and restores the o... | 02/05/2002 |
| 6343359 | Result forwarding cache An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics--complexity, power, and timing--that are not significantly impacted by the number of stages in the microproce... | 01/29/2002 |
| 6341343 | Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUs Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operan... | 01/22/2002 |
| 6330657 | Pairing of micro instructions in the instruction queue An apparatus and method are presented for increasing the throughput within a single-channel of a pipeline microprocessor. Back-to-back pairs of micro instructions are evaluated to determine if they can be combined for execution in parallel. If so, then th... | 12/11/2001 |
| 6324639 | Instruction converting apparatus using parallel execution code A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction... | 11/27/2001 |
| 6324640 | System and method for dispatching groups of instructions using pipelined register renaming Within a superscalar processor, multiple groups of instructions are dispatched simultaneously to a plurality of execution units. A renaming mechanism is utilized to permit out-of-order execution of these instructions within the multiple groups. The renami... | 11/27/2001 |
| 6314471 | Techniques for an interrupt free operating system A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, t... | 11/06/2001 |
| 6311266 | Instruction look-ahead system and hardware A method and system for executing instructions in a computer. Each instruction has a look-ahead code indicating the number of instructions after which may be executed before its own execution is completed. The look-ahead code increments a counter associat... | 10/30/2001 |
| 6308260 | Mechanism for self-initiated instruction issuing and method therefor An apparatus and method for self-initiated instruction issuing are implemented. In a central processing unit (CPU) having a pipelined architecture, instructions are queued for issuing to the execution unit which will execute them. Instructions are issued ... | 10/23/2001 |
| 6308254 | Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operations A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user instruction streams constituted with instructions of the ISA... | 10/23/2001 |
| 6308259 | Instruction queue evaluating dependency vector in portions during different clock phases An instruction queue is physically divided into two (or more) instruction queues. Each instruction queue is configured to store a dependency vector for each instruction operation stored in that instruction queue. The dependency vector is evaluated to dete... | 10/23/2001 |
| 6304953 | Computer processor with instruction-specific schedulers One embodiment of the present invention is a computer processor that includes a first scheduler adapted to dispatch a first type of computer instructions, and a second scheduler coupled to the first scheduler and adapted to dispatch a second type of compu... | 10/16/2001 |
| 6304959 | Simplified method to generate BTAGs in a decode unit of a processing system A method and system for assigning unique branch tag (BTAG) values in a decode unit in a processing system are disclosed. The method and system comprise providing at least one BTAG value and incrementing the at least one BTAG value for each fetch group as ... | 10/16/2001 |
| 6292845 | Processing unit having independent execution units for parallel execution of instructions of different category with instructions having specific bits indicating instruction size and category respectively An instruction fetching unit is described for loading instructions from a memory processed by a data processing device. The instruction code can be of at least two different lengths, and each instruction contains at least a single bit indicating said inst... | 09/18/2001 |
| 6292884 | Reorder buffer employing last in line indication A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the b... | 09/18/2001 |
| 6292882 | Method and apparatus for filtering valid information for downstream processing In one aspect, the invention includes an apparatus for filtering instructions within a digital system that eliminates the need to physically switch the valid instructions onto consecutive data lines of a buffer. The apparatus includes a filter for filteri... | 09/18/2001 |
| 6282635 | Method and apparatus for controlling an instruction pipeline in a data processing system An address translation memory stores a plurality of virtual address tags. The virtual address tags typically designate a portion of the virtual address space corresponding to a page of data stored in an intermediate storage device. A portion of an input v... | 08/28/2001 |
| 6272625 | Apparatus and method for processing events in a digital versatile disc (DVD) system using system threads and separate dormant/awake counter threads and clock driven semaphores A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not the system thread) increments and decrements the counter ... | 08/07/2001 |
| 6266745 | Method and system in a distributed shared-memory data processing system for determining utilization of nodes by each executed thread A method and system in a distributed shared-memory data processing system are disclosed for determining a utilization of each of a plurality of coupled processing nodes by one of a plurality of executed threads. The system includes a single operating syst... | 07/24/2001 |
| 6266765 | Computer architecture capable of execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued dur... | 07/24/2001 |
| 6260133 | Processor having operating instruction which uses operation units in different pipelines simultaneously An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also issues a normal ALU operating instruction to a second pipeline ... | 07/10/2001 |
| 6256726 | Data processor for the parallel processing of a plurality of instructions The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers i... | 07/03/2001 |
| 6256730 | Apparatus and method of processing counter parameters in a digital versatile disc system A multi-threaded digital versatile disc system which is controlled by a system thread includes an independent counter thread for controlling the counter parameters. Only the counter thread (and not the system thread) increments and decrements the counter ... | 07/03/2001 |
| 6247124 | Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information ... | 06/12/2001 |
| 6247120 | Instruction buffer for issuing instruction sets to an instruction decoder An instruction buffer includes a shift register having M storage elements to store instructions before the instructions are issued to an instruction decoder. The instruction buffer also includes control logic to issue the instructions from the shifter reg... | 06/12/2001 |
| 6237077 | Instruction template for efficient processing clustered branch instructions A method for processing one or more branch instructions in an instruction bundle is provided. The instructions are ordered in an execution sequence within the bundle, with the branch instructions ordered last in the sequence. The bundled instructions are ... | 05/22/2001 |
| 6237086 | 1 Method to prevent pipeline stalls in superscalar stack based computing systems An execution unit for a stack based computing system that can combine instructions into instruction groups for concurrent execution is provided. In accordance with one embodiment, the instructions of the stack based computing system are separated into dif... | 05/22/2001 |
| 6237082 | Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received A reorder buffer is configured into multiple lines of storage, wherein a line of storage includes sufficient storage for instruction results regarding a predefined maximum number of concurrently dispatchable instructions. A line of storage is allocated wh... | 05/22/2001 |
| 6233492 | Process control system and method for transferring process data therefor A process control system includes a plurality of machine controllers for individually controlling a plurality of process chambers and a main controller for controlling the machine controllers. Each of the machine controllers has a function of transferring... | 05/15/2001 |
| 6219780 | Circuit arrangement and method of dispatching instructions to multiple execution units A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor whenever it is determined that the producer instruction has... | 04/17/2001 |
| 6209081 | Method and system for nonsequential instruction dispatch and execution in a superscalar processor system A method and system for permitting nonsequential instruction dispatch in a superscalar processor system which dispatches sequentially ordered multiple instructions simultaneously to a group of execution units on an opportunistic basis for execution and pl... | 03/27/2001 |
| 6195744 | Unified multi-function operation scheduler for out-of-order execution in a superscaler processor A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to operations to be executed, being executed, or completed. ... | 02/27/2001 |
