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| Number | Title | Issue Date |
| 5434985 | Simultaneous prediction of multiple branches for superscalar processing System and method for predicting a multiplicity of future branches simultaneously (parallel) from an executing program, to enable the simultaneous fetching of multiple disjoint program segments. Additionally, the present invention detects divergence of in... | 07/18/1995 |
| 5430851 | Apparatus for simultaneously scheduling instruction from plural instruction streams into plural instruction execution units Disclosed is an information processor comprising multiple instruction setup units which fetch and decode instructions as the first half of the procedure in instruction pipelines, each of the instruction setup units being in charge of processing instructio... | 07/04/1995 |
| 5414822 | Method and apparatus for branch prediction using branch prediction table with improved branch prediction effectiveness The branch prediction using a branch prediction table formed by an associative memory which is applicable to a super scalar processor without causing confusion in the branch prediction. The branch prediction uses a branch prediction table for registering ... | 05/09/1995 |
| 5410657 | Method and system for high speed floating point exception enabled operation in a multiscalar processor system A method and system are disclosed for implementing floating point exception enabled operation without substantial performance degradation. In a multiscalar processor system, multiple instructions may be issued and executed simultaneously utilizing multipl... | 04/25/1995 |
| 5408658 | Self-scheduling parallel computer system and method An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for ... | 04/18/1995 |
| 5404469 | Multi-threaded microprocessor architecture utilizing static interleaving A static interleaving technique solves the problem of resource contention in a very long instruction word multi-threaded microprocessor architecture. In the static interleaving technique, each function unit in the processor is allocated for the execution ... | 04/04/1995 |
| 5404472 | Parallel processing apparatus and method capable of switching parallel and successive processing modes When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arit... | 04/04/1995 |
| 5394558 | Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions are executed in parallel by instruction execution units in a... | 02/28/1995 |
| 5390355 | Computer architecture capable of concurrent issuance and execution of general purpose multiple instructions A system for issuing a family of instructions during a single clock includes a decoder for decoding the family of instructions and logic, responsive to the decode result, for determining whether resource conflicts would occur if the family were issued dur... | 02/14/1995 |
| 5381533 | Dynamic flow instruction cache memory organized around trace segments independent of virtual address line An improved cache and organization particularly suitable for superscalar architectures. The cache is organized around trace segments of running programs rather than an organization based on memory addresses. A single access to the cache memory may cross v... | 01/10/1995 |
| 5377339 | Computer for simultaneously executing instructions temporarily stored in a cache memory with a corresponding decision result A computer for simultaneously executing plural instructions decides the kind of operation and the possibility of simultaneous execution for the plural instructions as the instructions are read out from a main memory to a cache memory. The plural instructi... | 12/27/1994 |
| 5371864 | Apparatus for concurrent multiple instruction decode in variable length instruction set computer A data processing apparatus for simultaneously reading out groups of two or more contiguous, variable length instructions from memory, and for decoding the group of variable length instructions in parallel. The data processing apparatus has a memory conta... | 12/06/1994 |
| 5355460 | In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instr... | 10/11/1994 |
| 5337415 | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency A system and method of producing predecode bits from instructions as instructions are copied from a memory system to a cache memory unit. A predecode unit, coupled between the memory unit and the cache memory unit, produces the predecode bits for utilizat... | 08/09/1994 |
| 5333280 | Parallel pipelined instruction processing system for very long instruction word A parallel pipelined instruction processing system for executing a plurality of instructions in parallel without no branch delay, comprises a instruction block fetch unit for fetching an instruction block including at least one instruction field and one b... | 07/26/1994 |
| 5301341 | Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions A mechanism is presented for detecting overflow in an interlock collapsing hardware apparatus that simultaneously executes two instructions. The overflow is determined as if the second instruction executes by itself using results from execution of the fir... | 04/05/1994 |
| 5287466 | Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks required to execute the instruction, and sort circuits that rearr... | 02/15/1994 |
| 5287465 | Parallel processing apparatus and method capable of switching parallel and successive processing modes When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arit... | 02/15/1994 |
| 5283874 | Cross coupling mechanisms for simultaneously completing consecutive pipeline instructions even if they begin to process at the same microprocessor of the issue fee Apparatus and methods for expediting the completion of microprocessor instructions using a microprocessor pipelining system. Two or more dependent instructions processed through two or more microprocessor pipelines are simultaneously completed. This simul... | 02/01/1994 |
| 5269007 | RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first compar... | 12/07/1993 |
| 5251306 | Apparatus for controlling execution of a program in a computing device An apparatus for controlling execution of a program of instructions in a computing device comprising an instruction fetching buffer-decoder for fetching the instructions in fetch batches and decoding the fetched instructions to generate a plurality of dec... | 10/05/1993 |
| 5241636 | Method for parallel instruction execution in a computer A method for parallel instruction execution in a computer is described. If the computer is executing in the single-instruction mode and the computer encounters a first type of instruction with a dual-instruction mode bit having a first value, then one mor... | 08/31/1993 |
| 5241633 | Instruction handling sequence control system for simultaneous execution of instructions An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or write... | 08/31/1993 |
| 5233694 | Pipelined data processor capable of performing instruction fetch stages of a plurality of instructions simultaneously The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers i... | 08/03/1993 |
| 5214763 | Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer sys... | 05/25/1993 |
| 5197135 | Memory management for scalable compound instruction set machines with in-memory compounding A digital computer system is described which is capable of processing 2 or more computer instructions in parallel and which has the capability of generating compounding tag information for those instructions, the compounding tag information being associat... | 03/23/1993 |
| 5185868 | Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy An apparatus for use with a computing device for executing instructions in a logical sequence according to a control program, comprises an instruction buffer of FIFO construction serially connected to a decoder buffer also of a FIFO construction. The deco... | 02/09/1993 |
| 5163139 | Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions An instruction memory apparatus for a data processing unit stores a sequence of instructions. At each instruction fetch cycle, two sequentially adjacent instructions are accessed. An instruction preprocessing unit, coupled to the internal instruction memo... | 11/10/1992 |
| 5136697 | System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory includes branch-prediction information fields in addition to in... | 08/04/1992 |
| 5129067 | Multiple instruction decoder for minimizing register port requirements A multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read p... | 07/07/1992 |
| 5072364 | Method and apparatus for recovering from an incorrect branch prediction in a processor that executes a family of instructions in parallel A branch recovery mechanism completes the processing of a concurrently issued family of instructions depending on the location of the branch instruction in the family and on whether the branch was correctly predicted. If the branch was not correctly predi... | 12/10/1991 |
| 5051885 | Data processing system for concurrent dispatch of instructions to multiple functional units Apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units. The instruction wor... | 09/24/1991 |
| 4903196 | Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently execu... | 02/20/1990 |
| 4807115 | Instruction issuing mechanism for processors with multiple functional units An instruction issuing mechanism for boosting throughput of processors with multiple functional units. A Dispatch Stack (DS) and a Precedence Count Memory (PCM) are employed which allow multiple instructions to be issued per machine cycle. Additionally, i... | 02/21/1989 |
| 4803615 | Microcode control of a parallel architecture microprocessor A microprogrammed parallel processor including a plurality of subprocessors operates under the control of microinstructions. Each microinstruction contains a plurality of micro-operations each of which requires one or more subprocessors for execution. All... | 02/07/1989 |
| 4736288 | Data processing device A data processing device which is equipped with a plurality of arithmetic units so that a plurality of instructions may be processed in parallel by the plural arithmetic units. The device includes a register control circuit for assigning one of a pluralit... | 04/05/1988 |
| 4720779 | Stored logic program scanner for a data processor having internal plural data and instruction streams A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of syllables in that code. The contents of these rams are signals i... | 01/19/1988 |
| 4639886 | Arithmetic system having pipeline structure arithmetic means An arithmetic system includes an arithmetic unit of a pipeline structure for executing arithmetic operations for instructions which require different arithmetic cycles. The arithmetic unit executes N arithmetics in pipeline for N instruction at maximum. I... | 01/27/1987 |
| 4574348 | High speed digital signal processor architecture A data processor uses complex instructions and a sequence controller to cause first and second fields of such instructions to process data, respectively, by first and second ALUs, with a third field of such instructions containing address information for ... | 03/04/1986 |
| 4295193 | Machine for multiple instruction execution A computing machine for concurrently executing instructions that have been compiled into a multi-instruction word comprised of a group of n instructions, where n is an integer. The group must not demand more than a predetermined number of data and instruc... | 10/13/1981 |
