Did You Know...
...that the video game, Pong, was invented by a guy who graduated at the bottom of his engineering class? Nolan Bushnell spent more time running the games at a local amusement park than he did on his studies at the University of Utah. His dreams of working for Disney's amusement empire were dashed when the company wouldn't hire him. Taking a boring job, Nolan daydreamed about electronic versions of popular games. He invented Pong, the first video game, and went on to found Atari Co.
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| Number | Title | Issue Date |
| 8108656 | Task definition for specifying resource requirements Task definitions are used by a task scheduler and prioritizer to allocate task operation to a plurality of processing units. The task definition is an electronic record that specifies researching needed by, and other characteristics of, a task to be executed. Resour... | 01/31/2012 |
| 8090930 | Method and circuits for early detection of a full queue In a pipelined computer architecture in which instructions may be removed from the instruction queue out of sequence, instruction queue status at a cycle K is determined by adding together the number of invalid instructions or free rows in the queue during cycle K�... | 01/03/2012 |
| 8082420 | Method and apparatus for executing instructions A method and apparatus for executing instructions in a processor are provided. In one embodiment of the invention, the method includes receiving a plurality of instructions. The plurality of instructions includes first instructions in a first thread and second instr... | 12/20/2011 |
| 8055883 | Pipe scheduling for pipelines based on destination register number A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process instructions. At least one instruction in... | 11/08/2011 |
| 8019973 | Information processing apparatus and method of controlling register An information processing apparatus and a method of controlling the same that employs a register window system and a Simultaneous Multithreading method for reducing circuit areas by sharing a data transfer bus between threads, said bus connecting a master register a... | 09/13/2011 |
| 7984270 | System and method for prioritizing arithmetic instructions The present invention provides a system and method for prioritizing arithmetic instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue g... | 07/19/2011 |
| 7953959 | Processor A processor includes: an instruction buffer which holds a group of instructions that can be executed in parallel; an instruction decoding unit which decodes part or all of the group of instructions; and an instruction issuance control unit which detects whether or n... | 05/31/2011 |
| 7949856 | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embo... | 05/24/2011 |
| 7921277 | Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit According to embodiments of the invention, there is disclosed a computer processor architecture; and in particular a computer processor, a method of operating the same, and a computer program product that makes use of an instruction set for the computer. In one embo... | 04/05/2011 |
| 7890734 | Mechanism for selecting instructions for execution in a multithreaded processor In one embodiment, a multithreaded processor includes a plurality of buffers, each configured to store instructions corresponding to a respective thread. The multithreaded processor also includes a pick unit coupled to the plurality of buffers. The pick unit may pic... | 02/15/2011 |
| 7890735 | Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture A multi-threaded microprocessor (1105) for processing instructions in threads. The microprocessor (1105) includes first and second decode pipelines (1730.0, 1730.1), first and second execute pipelines (1740, 1750), and coupling circuitry ... | 02/15/2011 |
| 7793080 | Processing pipeline having parallel dispatch and method thereof One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fet... | 09/07/2010 |
| 7721070 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 05/18/2010 |
| 7698535 | Asynchronous multiple-order issue system architecture An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a firs... | 04/13/2010 |
| 7636836 | Fetch and dispatch disassociation apparatus for multistreaming processors A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instructi... | 12/22/2009 |
| 7571301 | Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce... | 08/04/2009 |
| 7509483 | Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its functional execution flow. A compiled sequential HLL program's static con... | 03/24/2009 |
| 7475223 | Fetch-side instruction dispatch group formation An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping ... | 01/06/2009 |
| 7472257 | Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of execution units (160) via distrib... | 12/30/2008 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7437544 | Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processin... | 10/14/2008 |
| 7430643 | Multiple contexts for efficient use of translation lookaside buffer The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded p... | 09/30/2008 |
| 7430651 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags whi... | 09/30/2008 |
| 7430653 | Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a ... | 09/30/2008 |
| 7421571 | Apparatus and method for switching threads in multi-threading processors A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An ... | 09/02/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7409530 | Method and apparatus for compressing VLIW instruction and sharing subinstructions A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bit... | 08/05/2008 |
| 7406586 | Fetch and dispatch disassociation apparatus for multi-streaming processors A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one ... | 07/29/2008 |
| 7401204 | Parallel Processor efficiently executing variable instruction word A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units pe... | 07/15/2008 |
| 7401207 | Apparatus and method for adjusting instruction thread priority in a multi-thread processor Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the ... | 07/15/2008 |
| 7398374 | Multi-cluster processor for processing instructions of one or more instruction threads The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded”... | 07/08/2008 |
| 7395413 | System to dispatch several instructions on available hardware resources A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the e... | 07/01/2008 |
| 7395408 | Parallel execution processor and instruction assigning making use of group number in processing elements The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data... | 07/01/2008 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instruct... | 07/01/2008 |
| 7395532 | Process for running programs on processors and corresponding processor system Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of ins... | 07/01/2008 |
| 7380104 | Method and apparatus for back to back issue of dependent instructions in an out of order issue queue A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the pa... | 05/27/2008 |
| 7380107 | Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in respon... | 05/27/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exis... | 05/13/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
