Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 7636836 | Fetch and dispatch disassociation apparatus for multistreaming processors A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instructi... | 12/22/2009 |
| 7571301 | Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors A method for improving parallel processing of computer programs. DOACROSS loops and similar code are identified and parallelized using a post-wait control structure. The post-wait control structure may be implemented to include any one of a single counter to enforce... | 08/04/2009 |
| 7509483 | Methods and apparatus for meta-architecture defined programmable instruction fetch functions supporting assembled variable length instruction processors A computing architecture and software techniques are described which modifies the basic sequential instruction fetching mechanism of a processor by separating a program's control flow from its functional execution flow. A compiled sequential HLL program's static con... | 03/24/2009 |
| 7475223 | Fetch-side instruction dispatch group formation An improved method, apparatus, and computer instructions for grouping instructions. A set of instructions is received for placement into an instruction cache in the data processing system. Instructions in the set of instructions are grouped into a dispatch grouping ... | 01/06/2009 |
| 7472257 | Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of execution units (160) via distrib... | 12/30/2008 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7437544 | Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processin... | 10/14/2008 |
| 7430653 | Pipelined processor with multi-cycle grouping for instruction dispatch with inter-group and intra-group dependency checking A pipelined instruction dispatch or grouping circuit allows instruction dispatch decisions to be made over multiple processor cycles. In one embodiment, the grouping circuit performs resource allocation and data dependency checks on an instruction group, based on a ... | 09/30/2008 |
| 7430643 | Multiple contexts for efficient use of translation lookaside buffer The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded p... | 09/30/2008 |
| 7430651 | System and method for assigning tags to control instruction processing in a superscalar processor A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags whi... | 09/30/2008 |
| 7421571 | Apparatus and method for switching threads in multi-threading processors A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An ... | 09/02/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7409530 | Method and apparatus for compressing VLIW instruction and sharing subinstructions A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bit... | 08/05/2008 |
| 7406586 | Fetch and dispatch disassociation apparatus for multi-streaming processors A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one ... | 07/29/2008 |
| 7401204 | Parallel Processor efficiently executing variable instruction word A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units pe... | 07/15/2008 |
| 7401207 | Apparatus and method for adjusting instruction thread priority in a multi-thread processor Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the ... | 07/15/2008 |
| 7398374 | Multi-cluster processor for processing instructions of one or more instruction threads The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded”... | 07/08/2008 |
| 7395413 | System to dispatch several instructions on available hardware resources A processor (e.g., a co-processor) capable of executing instructions sequentially, comprises at least two functional hardware resources. When two instructions that are consecutive in program order and are executed on two separate functional hardware resources, the e... | 07/01/2008 |
| 7395408 | Parallel execution processor and instruction assigning making use of group number in processing elements The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data... | 07/01/2008 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instruct... | 07/01/2008 |
| 7395532 | Process for running programs on processors and corresponding processor system Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of ins... | 07/01/2008 |
| 7380104 | Method and apparatus for back to back issue of dependent instructions in an out of order issue queue A method is provided for evaluating two or more instructions in an out of order issue queue during a particular cycle of the queue, to select an instruction for issue during the next following cycle. If an instruction was previously designated to issue during the pa... | 05/27/2008 |
| 7380107 | Multi-processor system utilizing concurrent speculative source request and system source request in response to cache miss Multi-processor systems and methods are disclosed that employ speculative source requests to obtain speculative data fills in response to a cache miss. In one embodiment, a source processor generates a speculative source request and a system source request in respon... | 05/27/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exis... | 05/13/2008 |
| 7370179 | Microprocessor The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of compo... | 05/06/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
| 7366851 | Processor, method, and data processing system employing a variable store gather window A processor includes at least one instruction execution unit that executes store instructions to obtain store operations and a store queue coupled to the instruction execution unit. The store queue includes a queue entry in which the store queue gathers multiple sto... | 04/29/2008 |
| 7366874 | Apparatus and method for dispatching very long instruction word having variable length Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding u... | 04/29/2008 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic sp... | 04/29/2008 |
| 7366879 | Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor.... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7366884 | Context switching system for a multi-thread execution pipeline loop and method of operation thereof A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device reque... | 04/29/2008 |
| 7360062 | Method and apparatus for selecting an instruction thread for processing in a multi-thread processor The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave r... | 04/15/2008 |
| 7360220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two di... | 04/15/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
| 7350056 | Method and apparatus for issuing instructions from an issue queue in an information handling system An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue inc... | 03/25/2008 |
| 7343542 | Methods and apparatuses for variable length encoding Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality o... | 03/11/2008 |
| 7343479 | Method and apparatus for implementing two architectures in a chip The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles ... | 03/11/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |