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| Number | Title | Issue Date |
| 5987259 | Functional unit switching for the allocation of registers A method and apparatus for allocating registers when compiling code is provided. In response to determining there are insufficient registers associated with a first functional unit of a processor to allocate to a region of code, instructions associated wi... | 11/16/1999 |
| 5983336 | Method and apparatus for packing and unpacking wide instruction word using pointers and masks to shift word syllables to designated execution units groups An unpacking circuit and operating method in a very long instruction word (VLIW) processor provides for parallel handling of a packed wide instruction in which a packed wide instruction is divided into groups of syllables. An unpacked instruction represen... | 11/09/1999 |
| 5978896 | Method and system for increased instruction dispatch efficiency in a superscalar processor system A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatc... | 11/02/1999 |
| 5968166 | Information processing apparatus and method, and scheduling device for reducing inactivity due to wait state An information processing apparatus includes an instruction storage for storing a plurality of instructions and a central processing unit for fetching the instructions from the instruction storage device so as to execute the instructions. The central proc... | 10/19/1999 |
| 5968162 | Microprocessor configured to route instructions of a second instruction set to a second execute unit in response to an escape instruction A microprocessor is provided which detects an escape instruction. The escape instruction indicates that subsequent instructions belong to an alternate instruction set. In one embodiment, the number of subsequent instructions which belong to the alternate ... | 10/19/1999 |
| 5964862 | Execution unit and method for using architectural and working register files to reduce operand bypasses A CPU (central processing unit) of a computer. The CPU comprises a dispatch controller, a pipeline, a working register file, and an architectural register file. The dispatch controller dispatches instructions for execution and determines whether the dispa... | 10/12/1999 |
| 5961630 | Method and apparatus for handling dynamic structural hazards and exceptions by using post-ready latency A method for handling dynamic structural hazards and exceptions by using post-ready latency, including: receiving a plurality of instructions; selecting a first instruction whose execution can cause an exception; assigning a post-ready latency to a second... | 10/05/1999 |
| 5958041 | Latency prediction in a pipelined microarchitecture The present invention solves the problems associated with the prior art by providing a latency prediction bit (LPB) to indicate the latency with which an instruction should be executed, implicitly indicating whether a data dependency is likely to exist an... | 09/28/1999 |
| 5950009 | Method and apparatus for profile-based reordering of program portions in a computer program An apparatus and several methods provide for a more optimized computer program that will have a faster execution time than was possible using the prior art reordering technique that adds to a trace until it finds no more predecessors or successors to add.... | 09/07/1999 |
| 5944811 | Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an instruction parallel issue and execution administrating device ... | 08/31/1999 |
| 5944816 | Microprocessor configured to execute multiple threads including interrupt service routines A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is ca... | 08/31/1999 |
| 5941983 | Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then i... | 08/24/1999 |
| 5928355 | Apparatus for reducing instruction issue stage stalls through use of a staging register The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued f... | 07/27/1999 |
| 5920710 | Apparatus and method for modifying status bits in a reorder buffer with a large speculative state A superscalar microprocessor implements a reorder buffer to support out-of-order execution of instructions. To reduce the time delay for identifying mispredicted instructions, prioritizing mispredicted instructions, canceling instructions subsequent to th... | 07/06/1999 |
| 5918034 | Method for decoupling pipeline stages The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective pipeline. This permits the determination of whether a particular instruction can safely be issued f... | 06/29/1999 |
| 5898852 | Load instruction steering in a dual data cache microarchitecture An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first grou... | 04/27/1999 |
| 5889999 | Method and apparatus for sequencing computer instruction execution in a data processing system A method and apparatus for sequencing computer instructions in memory (24) to provide for more instruction efficient execution by a central processing unit (CPU) (22) begins by executing the computer instructions via the CPU (22) and creating a trace file... | 03/30/1999 |
| 5884058 | Method for concurrently dispatching microcode and directly-decoded instructions in a microprocessor A method of instruction dispatch is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During ... | 03/16/1999 |
| 5881253 | Computer system using posted memory write buffers in a bridge to implement system management mode A computer system using posted memory write buffers in a bridge can implement the system management mode without faulty operation. The system management interrupt acknowledge signal is posted in bridge buffers so that any previously posted memory write co... | 03/09/1999 |
| 5881261 | Processing system that rapidly indentifies first or second operations of selected types for execution A processing system includes sequential entries for storing operations of different types and a scan chain which can identify an operation of a first type which follows after an operation of a second type. The first and second types can be identical so th... | 03/09/1999 |
| 5872948 | Processor and method for out-of-order execution of instructions based upon an instruction parameter A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of th... | 02/16/1999 |
| 5867680 | Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions An instruction dispatch apparatus is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During... | 02/02/1999 |
| 5864341 | Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An ex... | 01/26/1999 |
| 5845100 | Dual instruction buffers with a bypass bus and rotator for a decoder of multiple instructions of variable length A circuit and method for supplying a block of instruction code to an instruction buffer for an instruction decoder. A block of instruction code is fetched and input through a buffer input. A first instruction buffer and a second instruction buffer are cou... | 12/01/1998 |
| 5838940 | Method and apparatus for rotating active instructions in a parallel data processor In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of the issue ordered instructions. The rotate and dispatch b... | 11/17/1998 |
| 5835747 | Hierarchical scan logic for out-of-order load/store execution control Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger store... | 11/10/1998 |
| 5835745 | Hardware instruction scheduler for short execution unit latencies A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from th... | 11/10/1998 |
| 5828880 | Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datum A pipelined process execution control system for multiprocessors is disclosed that enables multiple processors to cooperatively execute one or many software processes so that cache locality is not violated and extensive state, or context, information need... | 10/27/1998 |
| 5822559 | Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions A microprocessor is provided, including a plurality of early decode units configured to detect double dispatch instructions and to dispatch these instructions to a pair of decode units. More complex instructions are executed by an MROM unit in a serialize... | 10/13/1998 |
| 5822560 | Apparatus for efficient instruction execution via variable issue and variable control vectors per issue An apparatus employs a flexible instruction categorization scheme which includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instruct... | 10/13/1998 |
| 5805849 | Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions A data processor assigns a unique identifier to each instruction. As there are a finite number of unique identifiers, the identifiers are reused during execution of a program within the data processing system. To maintain an age relationship between instr... | 09/08/1998 |
| 5799165 | Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay A superscalar microprocessor includes a scheduler which contains storage for information related to operations and scan logic for selecting operations for out-of-order execution by a set of execution units. To provide fast operation, the selection is made... | 08/25/1998 |
| 5799163 | Opportunistic operand forwarding to minimize register file read ports Instruction issue rate is enhanced by passing multiple instructions to a read stage when the number of required source operands exceeds the read capability of a register file but operand forwarding reduces the number of reads required. The multiple instru... | 08/25/1998 |
| 5790822 | Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor A method and apparatus for executing instructions in a pipelined microprocessor. The method includes re-ordering the set of instructions prior to loading the instructions into an instruction cache. In one embodiment, a re-ordering unit receives the set of... | 08/04/1998 |
| 5774687 | Central processing unit detecting and judging whether operation result executed by ALU in response to a first instruction code meets a predetermined condition A central processing unit in a microprocessor, or the like, executes at high speed a simple program and sets a different immediate depending on a true or false state of a predetermined condition. In the central processing unit, the first and second immedi... | 06/30/1998 |
| 5764942 | Method and system for selective serialization of instruction processing in a superscalar processor system The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group o... | 06/09/1998 |
| 5761472 | Interleaving block operations employing an instruction set capable of delaying block-store instructions related to outstanding block-load instructions in a computer system A computer system which includes a processor having an instruction set capable of "delaying" block-store instructions related to any outstanding block-load instruction(s). Accordingly, a method for interleaving block data transfers and processing steps wh... | 06/02/1998 |
| 5754812 | Out-of-order load/store execution control Scheduler logic which tracks the relative age of stores with respect to a particular load (and of loads with respect to a particular store) allows a load-store execution controller constructed in accordance with the present invention to hold younger store... | 05/19/1998 |
| 5754811 | Instruction dispatch queue for improved instruction cache to queue timing A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, ... | 05/19/1998 |
| 5745725 | Parallel instruction execution with operand availability check during execution A succession of instructions are distributed between a plurality of multistage execution paths in a computer system. Each instruction is given a tag to identify the position of the instruction in the sequence and the execution paths of both that instructi... | 04/28/1998 |
