Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 5745726 | Method and apparatus for selecting the oldest queued instructions without data dependencies An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the a... | 04/28/1998 |
| 5708788 | Method for adjusting fetch program counter in response to the number of instructions fetched and issued A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program... | 01/13/1998 |
| 5689674 | Method and apparatus for binding instructions to dispatch ports of a reservation station A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the disp... | 11/18/1997 |
| 5684971 | Reservation station with a pseudo-FIFO circuit for scheduling dispatch of instructions A reservation station includes a memory array in which micro-operations are stored at entry locations with an age representing a temporal ordering. Control circuitry resets the age of a new micro-operation, and increments the ages of previously stored mic... | 11/04/1997 |
| 5682492 | Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The uni... | 10/28/1997 |
| 5682310 | Computer system including in-circuit emulation mode for debugging system management software A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls... | 10/28/1997 |
| 5669012 | Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of... | 09/16/1997 |
| 5669011 | Partially decoded instruction cache A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot con... | 09/16/1997 |
| 5640588 | CPU architecture performing dynamic instruction scheduling at time of execution within single clock cycle An apparatus and method for scheduling a sequence of instructions for achieving multiple launches and multiple executions of the instructions within a central processing unit. Each of the instructions is classified according to which one of multiple execu... | 06/17/1997 |
| 5630157 | Computer organization for multiple and out-of-order execution of condition code testing and setting instructions Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, inst... | 05/13/1997 |
| 5625788 | Microprocessor with novel instruction for signaling event occurrence and for providing event handling information in response thereto An out-of-order microprocessor signals event occurrence and provides event handling information utilizing a novel instruction issued to an execution unit upon detection of the condition giving rise to the event. Event information includes the type of even... | 04/29/1997 |
| 5613080 | Multiple execution unit dispatch with instruction shifting between first and second instruction buffers based upon data dependency A multiple execution unit processing system is provided wherein each execution unit has an associated instruction buffer and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second... | 03/18/1997 |
| 5577256 | Data driven type information processor including a combined program memory and memory for queuing operand data A data driven type information processor includes a control unit having a function of storing a data flow program and accessing it, and a function of producing an operand data pair, the control unit further including one memory shared by both functions. W... | 11/19/1996 |
| 5542061 | Arrangement of controlling issue timing of a read instruction to a common block in a vector processor In order to effectively accelerate issue of a RAM read instruction which is to access the same memory block as a preceding RAM write instruction, when the RAM write instruction is issued, a counter initiates counting-up of a value indicative a predetermin... | 07/30/1996 |
| 5504869 | High speed processing system capable of executing strings of instructions in order without waiting completion of previous memory access instruction An information processing system has a plurality of instruction strings containing a plurality of instructions and progressing process by executing instructions in one of the instruction strings in order. The system executes instructions in the instructio... | 04/02/1996 |
| 5428811 | Interface between a register file which arbitrates between a number of single cycle and multiple cycle functional units An interface protocol between a microprocessor register file (6) and a plurality of first functional units capable of independently executing first microinstructions that take a plurality of clock cycles to complete execution. A plurality of second functi... | 06/27/1995 |
| 5369775 | Data-flow processing system having an input packet limiting section for preventing packet input based upon a threshold value indicative of an optimum pipeline processing capacity A data-driven type computer system including an input limiting section for monitoring a current number of packets existing in the circular pipeline of the system while being processed. The input limiting section is adapted to control packets from being in... | 11/29/1994 |
| 5349692 | Instruction handling sequence control system for simultaneous execution of vector instructions An computer program instruction sequence control system to allow parallel or simultaneous execution of instructions. The system begins by loading two instructions for sequence determination. The system then checks if either instruction reads from or write... | 09/20/1994 |
| 5303356 | System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in t... | 04/12/1994 |
| 5295249 | Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer sys... | 03/15/1994 |
| 5276821 | Operation assignment method and apparatus therefor According to an assigning method and its apparatus having a resource use recording section for recording a use state of a resource necessary for executing given operations, a functional unit possession recording section for recording information represent... | 01/04/1994 |
| 5247628 | Parallel processor instruction dispatch apparatus with interrupt handler A data processing system for executing a sequence of instructions. The data processing system includes several processors each for executing instructions. Also included is a dispatching apparatus for dispatching each of the instructions to one of the proc... | 09/21/1993 |
| 5127093 | Computer look-ahead instruction issue control A system for scheduling instruction issuance in a vector register computer achieves increased efficiency of operation by performing pre-issuance checks to determine if resources requested by the instruction will be available when the instruction issues. A... | 06/30/1992 |
| 4916652 | Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number... | 04/10/1990 |
| 4858176 | Distributor of machine words between units of a central processor A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands... | 08/15/1989 |
| 4837678 | Instruction sequencer for parallel operation of functional units An instruction sequencer for programming parallel operations of functional units in response to an instruction stream is shown. The instruction sequencer includes a random access memory for storing instruction segments which program the operations of the ... | 06/06/1989 |
| 4837688 | Multi-channel shared resource processor An external dispatcher distributes prioritize tasks to a plurality of processor channels. The processor channels then contend for one of two partitions for the execution of instructions assigned thereto during a multiphase instruction cycle. Two unique pr... | 06/06/1989 |
| 4811215 | Instruction execution accelerator for a pipelined digital machine with virtual memory An instruction execution accelerator for a pipelined digital machine with virtual memory. The digital machine includes a pipelined processor which on memory accesses outputs a virtual address to a data cache unit (DCU). On particular memory accesses, such... | 03/07/1989 |
| 4763294 | Method and apparatus for floating point operations An information processing system having a memory for storing instructions and operands, a central processor unit which includes a mechanism for fetching and decoding instructions and operands and a bus connected between the processor unit and memory. An a... | 08/09/1988 |
| 4707783 | Ancillary execution unit for a pipelined data processing system An ancillary execution unit is interfaced to a primary execution unit of a data processing system where the ancillary unit operates faster than the primary for certain instructions and allows for bypassing the slower unit. The primary execution unit has a... | 11/17/1987 |
| 4701847 | Adaptive instruction sequence synthesizer and process An apparatus and method for adaptively generating instructions for use by the central processing unit (CPU) of a computer. Upon detection of a start up signal pattern on the computer's system bus, instructions are generated in response to memory access si... | 10/20/1987 |
| 4600991 | Integrated microprogrammed device for controlling information processing cycles, and a method for operating the same An integrated microprogrammed device for controlling information processing cycles, includes a device for generating one or more T-states in dependence on preceding T-states and on given parameters and a method for operating the device.... | 07/15/1986 |
| 4597044 | Apparatus and method for providing a composite descriptor in a data processing system In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM... | 06/24/1986 |
| 4493020 | Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource al... | 01/08/1985 |
| 4225920 | Operator independent template control architecture In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the... | 09/30/1980 |
| 4197579 | Multi-processor for simultaneously executing a plurality of programs in a time-interlaced manner A computer processor is described capable of simultaneously executing a plurality of programs. It accomplishes this by utilizing the next instruction select elements of a processor to select the next instruction for one program, while the data processing ... | 04/08/1980 |
| 4153941 | Timing circuit and method for controlling the operation of cyclical devices An electronic data processing system which utilizes a variable timing period that is varied in accordance with the access time of the digital devices or circuits utilized in each step of the data processing program. In one embodiment, the data processing ... | 05/08/1979 |
| 4152763 | Control system for central processing unit with plural execution units In a multi-processor where an execution unit is shared with a plurality of instruction control units, a control system for the multi-processor includes small-scale execution units provided corresponding to the instruction control units, each small-scale e... | 05/01/1979 |
| 3932845 | Specialized digital computer with divided memory and arithmetic units A specialized digital computer, adapted to carry out a specific and delimited range of functions with respect to its application, comprises separate and functionally different stores including: a program store, an input-output buffer store, a permanent-da... | 01/13/1976 |
