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Pizza Pie With Concentric Rings of Crust
A pizza mold for forming a plurality of concentric raised ridges of dough (i.e., crust) on the surface of a pizza pie.
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| Number | Title | Issue Date |
| 8185722 | Processor instruction set for controlling threads to respond to events The invention provides a processor comprising an execution unit and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective status for each thread. The execution unit is configured to execute... | 05/22/2012 |
| 8176298 | Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 05/08/2012 |
| 8171261 | Method and system for accessing memory in parallel computing using load fencing instructions A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory or... | 05/01/2012 |
| 8140829 | Multithreaded processor and method for switching threads by swapping instructions between buffers while pausing execution A processor includes primary threads of execution that may simultaneously issue instructions, and one or more backup threads. When a primary thread stalls, the contents of its instruction buffer may be switched with the instruction buffer for a backup thread, thereb... | 03/20/2012 |
| 8140830 | Structural power reduction in multithreaded processor A circuit arrangement and method utilize a plurality of execution units having different power and performance characteristics and capabilities within a multithreaded processor core, and selectively route instructions having different performance requirements to dif... | 03/20/2012 |
| 8127114 | System and method for executing instructions prior to an execution stage in a processor A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to t... | 02/28/2012 |
| 8112616 | Reduced instruction set baseband controller In wireless communications such as in the Bluetooth communication system, an execution unit sequentially receives software instructions for execution. Prior to completing each instruction, the execution unit issues an interrupt indicating the upcoming completion of ... | 02/07/2012 |
| 8108655 | Selecting fixed-point instructions to issue on load-store unit Issue logic identifies a simple fixed point instruction, included in a unified payload, which is ready to issue. The simple fixed point instruction is a type of instruction that is executable by both a fixed point execution unit and a load-store execution unit. In t... | 01/31/2012 |
| 8108654 | System and method for a group priority issue schema for a cascaded pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in ... | 01/31/2012 |
| 8095779 | System and method for optimization within a group priority issue schema for a cascaded pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in ... | 01/10/2012 |
| 8095778 | Method and system for sharing functional units of a multithreaded processor Sharing functional units within a multithreaded processor. In one embodiment, the multithreaded processor may include a multithreaded instruction source that may provide an instruction from each of a plurality of thread groups in a given cycle. A given thread group ... | 01/10/2012 |
| 8086825 | Processing pipeline having stage-specific thread selection and method thereof One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fet... | 12/27/2011 |
| 8086826 | Dependency tracking for enabling successive processor instructions to issue An information handling system includes a processor with an issue unit (IU) that may perform instruction dependency tracking for successive instruction issue operations. The IU maintains non-shifting issue queue (NSIQ) and shifting issue queue (SIQ) instructions alo... | 12/27/2011 |
| 8074056 | Variable length pipeline processor architecture In one implementation, a pipeline processor is provided having a base architecture that includes one or more decoders operable to decode program instructions and generate one or more decoded instructions, and one or more execution units operable to execute the one o... | 12/06/2011 |
| 8051275 | Result path sharing between a plurality of execution units within a processor A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determine... | 11/01/2011 |
| 7996654 | System and method for optimization within a group priority issue schema for a cascaded pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in ... | 08/09/2011 |
| 7991979 | Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier fi... | 08/02/2011 |
| 7984268 | Advanced processor scheduling in a multithreaded system An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 07/19/2011 |
| 7984269 | Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instruction A data processing apparatus and method are provided for executing complex instructions. The data processing apparatus executes instructions defining operations to be performed by the data processing apparatus, those instructions including at least one complex instru... | 07/19/2011 |
| 7979677 | Adaptive allocation of reservation station entries to an instruction set with variable operands in a microprocessor A method and device for adaptively allocating reservation station entries to an instruction set with variable operands in a microprocessor. The device includes logic for determining free reservation station queue positions in a reservation station. The device alloca... | 07/12/2011 |
| 7966477 | Power optimized replay of blocked operations in a pipilined architecture A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a... | 06/21/2011 |
| 7949855 | Scheduler in multi-threaded processor prioritizing instructions passing qualification rule A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation and at least one memory access operation. Instructions within each ph... | 05/24/2011 |
| 7945764 | Processing unit incorporating multirate execution unit A multirate execution unit is capable of being operated in a plurality of modes, with the execution unit being capable of clocked at multiple different rates relative to a multithreaded issue unit such that, in applications where maximum performance is desired, the ... | 05/17/2011 |
| 7941644 | Simultaneous multi-thread instructions issue to execution units while substitute injecting sequence of instructions for long latency sequencer instruction via multiplexer A processing unit includes multiple execution units and sequencer logic that is disposed downstream of instruction buffer logic, and that is responsive to a sequencer instruction present in an instruction stream. In response to such an instruction, the sequencer log... | 05/10/2011 |
| 7941642 | Method for selecting between divide instructions associated with respective threads in a multi-threaded processor In one embodiment, a multithreaded processor includes a multithreaded instruction source that may provide a plurality of instructions each corresponding to a respective one of a plurality of threads. The multithreaded processor also includes a pick unit coupled to t... | 05/10/2011 |
| 7941643 | Multi-thread processor with multiple program counters A system, apparatus and method for an interleaving multi-thread processing device are described herein. The multi-thread processing device includes an execution block to execute instructions and a fetch block to fetch and issue instructions, interleavingly, of a fir... | 05/10/2011 |
| 7937563 | Voltage droop mitigation through instruction issue throttling A system and method for providing a digital real-time voltage droop detection and subsequent voltage droop reduction. A scheduler within a reservation station may store a weight value for each instruction corresponding to node capacitance switching activity for the ... | 05/03/2011 |
| 7937562 | Processing apparatus A processing apparatus includes an execution stage which executes each of instruction streams, a first resource counter which counts the number of operating resources used when the execution stage executes a first one of the instruction streams, a second resource co... | 05/03/2011 |
| 7861062 | Data processing device with instruction controlled clock speed The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functio... | 12/28/2010 |
| 7861065 | Preferential dispatching of computer program instructions A computer processor that includes a plurality of execution pipelines, each execution pipeline including a configuration of one or more execution units of the processor, each execution pipeline characterized by an execution pipeline type, each execution pipeline typ... | 12/28/2010 |
| 7861063 | Delay slot handling in a processor In one embodiment, a processor comprises a fetch unit and a pick unit. The fetch unit is configured to fetch instructions for execution by the processor. The pick unit is configured to schedule instructions fetched by the fetch unit for execution in the processor. T... | 12/28/2010 |
| 7861064 | Method, system, and computer program product for selectively accelerating early instruction processing A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instructio... | 12/28/2010 |
| 7853777 | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicato... | 12/14/2010 |
| 7797514 | Scalable multi-threaded sequencing/synchronizing processor architecture A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory. ... | 09/14/2010 |
| 7779235 | Using performance data for instruction thread direction A method for dispatching instructions in the data processing system, having in memory for storing instructions and a plurality of central processing units, where each central processing unit includes a circuit to provide data indicating internal performance, the met... | 08/17/2010 |
| 7769984 | Dual-issuance of microprocessor instructions using dual dependency matrices A dual-issue instruction is decoded to determine a plurality of LSU dependencies needed by an LSU part of the dual-issue instruction and a plurality of non-LSU dependencies needed by a non-LSU part of the dual-issue instruction. During dispatch of the dual-issue ins... | 08/03/2010 |
| 7761690 | Method, apparatus and computer program product for dynamically selecting compiled instructions A method, apparatus, and computer program product dynamically select compiled instructions for execution. Static instructions for execution on a first execution and dynamic instructions for execution on a second execution unit are received. The throughput performanc... | 07/20/2010 |
| 7739483 | Method and apparatus for increasing load bandwidth A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture. ... | 06/15/2010 |
| 7725683 | Apparatus and method for power optimized replay via selective recirculation of instructions A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a... | 05/25/2010 |
| 7725684 | Speculative instruction issue in a simultaneously multithreaded processor A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic sp... | 05/25/2010 |
