Quotables
"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8145883 | Preloading instructions from an instruction set other than a currently executing instruction set A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set... | 03/27/2012 |
| 8037286 | Data processing apparatus and method for instruction pre-decoding The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding oper... | 10/11/2011 |
| 8001361 | Structure for a single shared instruction predecoder for supporting multiple processors A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for improved techniques for executing instructions in a pipelined manner is provided. Such techniques may reduce stalls that occur when executing d... | 08/16/2011 |
| 7962725 | Pre-decoding variable length instructions A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a prop... | 06/14/2011 |
| 7945763 | Single shared instruction predecoder for supporting multiple processors Improved techniques for executing instructions in a pipelined manner that may reduce stalls that occur when executing dependent instructions are provided. Stalls may be reduced by utilizing a cascaded arrangement of pipelines with execution units that are delayed wi... | 05/17/2011 |
| 7925866 | Data processing apparatus and method for handling instructions to be executed by processing circuitry A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-deco... | 04/12/2011 |
| 7925867 | Pre-decode checking for pre-decoded instructions that cross cache line boundaries A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instr... | 04/12/2011 |
| 7917735 | Data processing apparatus and method for pre-decoding instructions A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decod... | 03/29/2011 |
| 7877578 | Processing apparatus for storing branch history information in predecode instruction cache The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information indicating that the input instruction is a conditional branch instruction... | 01/25/2011 |
| 7769983 | Caching instructions for a multiple-state processor A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is... | 08/03/2010 |
| 7747839 | Data processing apparatus and method for handling instructions to be executed by processing circuitry A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-deco... | 06/29/2010 |
| 7730281 | System and method for storing immediate data An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field. ... | 06/01/2010 |
| 7711927 | System, method and software to preload instructions from an instruction set other than one currently executing An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding i... | 05/04/2010 |
| 7647478 | Suppression of store checking An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruc... | 01/12/2010 |
| 7647479 | Non-temporal memory reference control mechanism An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extende... | 01/12/2010 |
| 7509481 | Patchable and/or programmable pre-decode Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a programmable pre-decode mechanism can be employed to alter the behavior of a processor. For examp... | 03/24/2009 |
| 7487334 | Branch encoding before instruction cache write Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes performing at least one pre-calculation relating to determining the ... | 02/03/2009 |
| 7441104 | Parallel subword instructions with distributed results The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify (implicitly or explicitly) a bit position and the result of each of the para... | 10/21/2008 |
| 7415638 | Pre-decode error handling via branch correction In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is force... | 08/19/2008 |
| 7395412 | Apparatus and method for extending data modes in a microprocessor An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation... | 07/01/2008 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instruct... | 07/01/2008 |
| 7376815 | Methods and apparatus to insure correct predecode Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest le... | 05/20/2008 |
| 7366874 | Apparatus and method for dispatching very long instruction word having variable length Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding u... | 04/29/2008 |
| 7360060 | Using IMPDEP2 for system commands related to Java accelerator hardware A processor (e.g., a co-processor) comprising a decoder adapted to decode instructions from a first instruction set in a first mode and a second instruction set in a second mode. A pre-decoder coupled to the decoder, and operates in parallel with the decoder, determ... | 04/15/2008 |
| 7356673 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of exe... | 04/08/2008 |
| 7353363 | Patchable and/or programmable decode using predecode selection Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, ... | 04/01/2008 |
| 7346760 | Data processing apparatus of high speed process using memory of low speed and low power consumption When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory... | 03/18/2008 |
| 7343478 | Register window system and method that stores the next register window in a temporary buffer The present apparatus reduces hardware resources and improves data read throughput in an information processing apparatus employing the out-of-order instruction execution method. The apparatus includes: an arithmetic operation unit which executes a window switching ... | 03/11/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7343482 | Program subgraph identification There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said pro... | 03/11/2008 |
| 7343473 | System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The s... | 03/11/2008 |
| 7343479 | Method and apparatus for implementing two architectures in a chip The present invention is a method for implementing two architectures on a single chip. The method uses a fetch engine to retrieve instructions. If the instructions are macroinstructions, then it decodes the macroinstructions into microinstructions, and then bundles ... | 03/11/2008 |
| 7340587 | Information processing apparatus, microcomputer, and electronic computer An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch i... | 03/04/2008 |
| 7340589 | Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a de... | 03/04/2008 |
| 7334111 | Method and related device for use in decoding executable code The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling code at run-time, and including the steps of dividing the code into ... | 02/19/2008 |
| 7328328 | Non-temporal memory reference control mechanism An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extende... | 02/05/2008 |
| 7321963 | System and method for storing immediate data An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field. ... | 01/22/2008 |
| 7318218 | System and method for processor thread for software debugging A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger threa... | 01/08/2008 |
| 7305542 | Instruction length decoder Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor cl... | 12/04/2007 |
| 7305676 | Communication device configured for real time processing of user data to be transmitted A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned ... | 12/04/2007 |
