Quotables
"This is the patent age of new inventions for killing bodies, and for saving souls. All propagated with the best intentions."
Lord Byron ;
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8078842 | Removing local RAM size limitations when executing software code An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first grou... | 12/13/2011 |
| 8037285 | Trace unit An instruction processing circuit includes a decoder circuit operable to receive a sequence of instructions and to decode the received sequence of instructions into a first type of sequence of operations, and a trace builder circuit operable to receive at least a po... | 10/11/2011 |
| 7831807 | System and method for expanding the instruction set of an instruction processor A system and method for modifying the hardware instruction set of an instruction processor is disclosed. The invention utilizes one or more bits of an instruction opcode and one or more programmable bits stored within the instruction processor to generate a branch a... | 11/09/2010 |
| 7743232 | Multiple-core processor with hierarchical microcode store A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may inclu... | 06/22/2010 |
| 7694110 | System and method of implementing microcode operations as subroutines Various embodiments of methods and systems for implementing a set of microcode operations corresponding to a microcoded instruction as a microcode subroutine are disclosed. In one embodiment, a microprocessor includes a dispatch unit configured to dispatch operation... | 04/06/2010 |
| 7398372 | Fusing load and alu operations Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops ... | 07/08/2008 |
| 7398376 | Instructions for ordering execution in pipelined processes Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and plac... | 07/08/2008 |
| 7366891 | Methods and apparatus to provide dual-mode drivers in processor systems Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers... | 04/29/2008 |
| 7356456 | Computer storage exception handing apparatus and method for virtual hardware system In a design system using virtual hardware models, a filtering manager for filtering execution results and determining which software instructions are candidates for restructuring. In some examples, illegal address range instructions are identified based on exception... | 04/08/2008 |
| 7334109 | Method and apparatus for improving segmented memory addressing A method and apparatus for breaking complex X86 segment operations and segmented addressing into explicit sub-operations so that they may be exposed to compiler or translator-based optimizations. ... | 02/19/2008 |
| 7321963 | System and method for storing immediate data An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field. ... | 01/22/2008 |
| 7290120 | Microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor based on the inventive architecture has a power-saving fetch and deco... | 10/30/2007 |
| 7290081 | Apparatus and method for implementing a ROM patch using a lockable cache A ROM patching apparatus for use in a data processing system that executes instruction code stored in the ROM. The ROM patching apparatus comprises: 1) a patch buffer for storing a first replacement cache line containing a first new instruction suitable for replacin... | 10/30/2007 |
| 7283557 | Asynchronous crossbar with deterministic or arbitrated control Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an... | 10/16/2007 |
| 7281121 | Pipeline processing device and interrupt processing method At an MA stage, data, such as a header address of an interrupt processing routine, is loaded via a data bus and immediately supplied to a program counter via multiplexers without the intervention of an instruction decode stage in accordance with a setting address ou... | 10/09/2007 |
| 7274710 | Asynchronous crossbar with deterministic or arbitrated control Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an... | 09/25/2007 |
| 7274709 | Asynchronous crossbar with deterministic or arbitrated control Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an... | 09/25/2007 |
| 7266038 | Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a sel... | 09/04/2007 |
| 7240179 | System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is ina... | 07/03/2007 |
| 7236106 | Methods and systems for data manipulation A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operati... | 06/26/2007 |
| 7213126 | Method and processor including logic for storing traces within a trace cache A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be ass... | 05/01/2007 |
| 7204417 | Graphical code reader that is configured for efficient decoder management A graphical code reader is disclosed. The graphical code reader includes a processor and memory in electronic communication with the processor. The memory is used for storing a digital image of a graphical code. The graphical code reader also includes a plurality of... | 04/17/2007 |
| 7206921 | Micro-operation un-lamination A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type oper... | 04/17/2007 |
| 7197628 | Method and apparatus for execution flow synonyms A method and apparatus for utilizing multiple microcode flow synonyms or hardware flow synonyms for an instruction is disclosed. In one embodiment, a microcode synonym is created for execution on two or more execution units of differing types. One microcode synonym ... | 03/27/2007 |
| 7191314 | Reconfigurable CPU with second FSM control unit executing modifiable instructions A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one... | 03/13/2007 |
| 7162621 | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 01/09/2007 |
| 7143265 | Computer program product memory access system A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively wi... | 11/28/2006 |
| 7139897 | Computer instruction dispatch Circuit arrangement and method for dispatching computer instructions. In a processor having a plurality of types of execution units, the computer instructions are grouped in bundles, and each bundle includes a plurality of instructions and an associated index code. ... | 11/21/2006 |
| 7131118 | Write-through caching a JAVA® local variable within a register of a register bank In a data processing apparatus 2 having a first mode of operation in which JAVA® bytecodes 46, 48 specify the processing operations and a second mode of operation in which other instructions specify the processing operations. In order to speed operati... | 10/31/2006 |
| 7124280 | Execution control apparatus of data driven information processor for instruction inputs An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one addr... | 10/17/2006 |
| 7114057 | System and method for storing immediate data An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field. ... | 09/26/2006 |
| 7111148 | Method and apparatus for compressing relative addresses A method and apparatus for compressing relative addresses and for storage of compressed relative addresses. A relative virtual address is computed in a particular stage of a processor pipeline and then compressed according to one or more compression techniques for s... | 09/19/2006 |
| 7111151 | Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The m... | 09/19/2006 |
| 7107439 | System and method of controlling software decompression through exceptions When processor instructions are required for execution, a misaligned address is sent to the processor. The misaligned instruction address causes a computer processor exception. The computer system automatically executes an exception handling routine that transforms ... | 09/12/2006 |
| 7107434 | System, method and apparatus for allocating hardware resources using pseudorandom sequences The present invention provides a system, method and apparatus for allocating resources by assigning resource identifiers to processor resources using at least a portion of a pseudorandom sequence. One or more resource identifiers are generated using at least a porti... | 09/12/2006 |
| 7103736 | System for repair of ROM programming errors or defects A system is disclosed for use of imperfect ROMs in embedded systems. The ROM or other memory accessible upon start-up of the system, includes a stored program which checks an external source to determine whether any of the information in the ROM should be replaced. ... | 09/05/2006 |
| 7069421 | Side tables annotating an instruction stream A microprocessor chip, and methods for use in that microprocessor chip. The chip has instruction pipeline circuitry and address translation circuitry. Table lookup circuitry indexes into a table, the table having an entry associated with each corresponding address r... | 06/27/2006 |
| 7062598 | Bypass custom array and related method for implementing ROM fixes in a data processor A processing system comprising: i) a read-only memory (ROM) that stores original ROM code; ii) a custom array that stores replacement ROM code; and iii) control logic that receives an incoming ROM address and a read request signal generated by a source device. The c... | 06/13/2006 |
| 7050324 | Asynchronous static random access memory A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRA... | 05/23/2006 |
| 6975250 | Methods and systems for data manipulation A method of and device for performing a data expansion operation on a plurality of input data objects to generate expanded output data objects is disclosed. The method comprises receiving and decoding a data manipulation instruction defining a data expansion operati... | 12/13/2005 |
