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| Number | Title | Issue Date |
| 8161269 | Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opco... | 04/17/2012 |
| 8131978 | Restoring plural instructions for same cycle execution from partial instructions and combined supplementing portions generated for compact storage An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some o... | 03/06/2012 |
| 8006071 | Processors operable to allow flexible instruction alignment Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across diffe... | 08/23/2011 |
| 7979676 | Method for instructing a data processor to process data A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a siz... | 07/12/2011 |
| 7966476 | Determining length of instruction with escape and addressing form bytes without evaluating opcode A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opco... | 06/21/2011 |
| 7917734 | Determining length of instruction with multiple byte escape code based on information from other than opcode byte A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opco... | 03/29/2011 |
| 7908463 | Immediate and displacement extraction and decode mechanism An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit... | 03/15/2011 |
| 7895414 | Instruction length determination device and method using concatenate bits to determine an instruction length in a multi-mode processor An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determi... | 02/22/2011 |
| 7865699 | Method and apparatus to extend the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 01/04/2011 |
| RE41959 | Variable address length compiler and processor improved in address management The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the conver... | 11/23/2010 |
| 7818543 | Method and apparatus for length decoding and identifying boundaries of variable length instructions A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructi... | 10/19/2010 |
| 7818542 | Method and apparatus for length decoding variable length instructions A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be... | 10/19/2010 |
| RE41751 | Instruction converting apparatus using parallel execution code A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The numbe... | 09/21/2010 |
| 7734898 | System and method for specifying an immediate value in an instruction A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of th... | 06/08/2010 |
| 7711926 | Mapping system and method for instruction set processing A method, cache controller, and computer processor provide a parallel mapping system whereby a plurality of mappers processes several inputs simultaneously. The plurality of mappers are disposed in a pipelined processor upstream from a multiplexor. Mapping, tag comp... | 05/04/2010 |
| 7689811 | Method and apparatus for constant generation in SIMD processing A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a d... | 03/30/2010 |
| 7676653 | Compact instruction set encoding The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input... | 03/09/2010 |
| 7676654 | Extended register space apparatus and methods for processors Methods and apparatus for accessing an extended register space associated with a processor are disclosed. In an example method, an instruction indicating a tag value is received. It is then determined whether information is stored in a first group of registers or a ... | 03/09/2010 |
| 7676652 | Executing variable length instructions stored within a plurality of discrete memory address regions Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length ... | 03/09/2010 |
| 7676651 | Micro controller for decompressing and compressing variable length codes via a compressed code dictionary The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion inf... | 03/09/2010 |
| 7664934 | Data processor decoding instruction formats using operand data A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a regis... | 02/16/2010 |
| 7664935 | System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The s... | 02/16/2010 |
| 7581083 | Operation processing device, system and method having register-to-register addressing As shown in FIG. 1, an operation-processing device of the present invention comprises a register array (11) having plural registers for holding an arbitrary value based on a write address Aw and a write control signal Sw and outputting this value based... | 08/25/2009 |
| RE40883 | Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half conta... | 08/25/2009 |
| 7581084 | Method and apparatus for efficient loading and storing of vectors A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. Th... | 08/25/2009 |
| 7543134 | Apparatus and method for extending a microprocessor instruction set An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended in... | 06/02/2009 |
| 7529912 | Apparatus and method for instruction-level specification of floating point format Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic... | 05/05/2009 |
| 7526633 | Method and system for encoding variable length packets with variable instruction sizes Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encodin... | 04/28/2009 |
| 7523294 | Maintaining original per-block number of instructions by inserting NOPs among compressed instructions in compressed block of length compressed by predetermined ratio The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to Huffman-Encoding technique; determining whether it's necessary to insert no-operati... | 04/21/2009 |
| 7502911 | Variable length instruction fetching that retrieves second instruction in dependence upon first instruction length A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. P... | 03/10/2009 |
| 7424597 | Variable reordering (Mux) instructions for parallel table lookups from registers Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify t... | 09/09/2008 |
| RE40498 | Variable address length compiler and processor improved in address management The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the conver... | 09/09/2008 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction ... | 09/02/2008 |
| 7380103 | Apparatus and method for selective control of results write back A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructi... | 05/27/2008 |
| 7376814 | Method for forming variable length instructions in a processing system Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the ... | 05/20/2008 |
| 7372378 | Efficient decoding of n-tuple variable bit length symbols Methods and systems that leverage the advantages of Huffman coding to increase processing efficiency of a data-stream while simultaneously minimizing storage requirements are provided. Decoding efficiency and table storage requirements can be balanced to produce sys... | 05/13/2008 |
| 7373483 | Mechanism for extending the number of registers in a microprocessor An apparatus and method are provided, for accessing extended registers within a microprocessor. The apparatus includes translation logic and extended register logic. The translation logic translates an extended instruction into corresponding micro instructions for e... | 05/13/2008 |
| 7366876 | Efficient emulation instruction dispatch based on instruction width In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7366881 | Method and apparatus for staggering execution of an instruction A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two lo... | 04/29/2008 |
