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| Number | Title | Issue Date |
| 8051273 | Supplying instruction stored in local memory configured as cache to peer processing elements in MIMD processing units Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, whic... | 11/01/2011 |
| 7356676 | Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a copr... | 04/08/2008 |
| 7340591 | Providing parallel operand functions using register file and extra path storage A number of architectural and implementation approaches are described for using extra path (Epath) storage that operate in conjunction with a compute register file to obtain increased instruction level parallelism that more flexibly addresses the requirements of hig... | 03/04/2008 |
| 7330964 | Microprocessor with independent SIMD loop buffer An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected b... | 02/12/2008 |
| 7313646 | Interfacing of functional modules in an on-chip system An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface... | 12/25/2007 |
| 7305499 | DMA controller for controlling and measuring the bus occupation time value for a plurality of DMA transfers The present invention provides a DMA transfer controller includes: a transfer parameter storing unit for storing a bus occupation time value and transfer parameters of one set or a plurality of sets of DMA transfers for each of a plurality of logical processors; a d... | 12/04/2007 |
| 7254695 | Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors A coprocessor instruction interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of multiple coprocessing instruction interfaces with a single coprocessor for supp... | 08/07/2007 |
| 7243282 | Method and apparatus for implementing multiple remote diagnose register chains Method and apparatus for implementing a plurality of RDR chains, wherein each of the RDR chains comprises at least one RDR is described. In one embodiment, the method comprises, responsive to execution of a first instruction identifying one of the RDR chains and one... | 07/10/2007 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 06/19/2007 |
| 7216252 | Method and apparatus for machine check abort handling in a multiprocessing system In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A ma... | 05/08/2007 |
| 7206904 | Method and system for buffering multiple requests from multiple devices to a memory A system for sharing a computational resource by buffering multiple requests from multiple devices to a memory (e.g. a multi-port RAM or FIFO) in a single clock cycle. The system includes a memory having a first write port and a second write port. A first request in... | 04/17/2007 |
| 7197498 | Apparatus, system and method for updating a sorted list A method, apparatus, and system for updating a sorted list. ... | 03/27/2007 |
| 7191310 | Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processin... | 03/13/2007 |
| 7185128 | System and method for machine specific register addressing in external devices There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus device... | 02/27/2007 |
| 7143401 | Single-chip multiprocessor with cycle-precise program scheduling of parallel execution A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register f... | 11/28/2006 |
| 7124318 | Multiple parallel pipeline processor having self-repairing capability A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferab... | 10/17/2006 |
| 7117419 | Reliable communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 10/03/2006 |
| 7103823 | Communication between multi-processor clusters of multi-cluster computer systems Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnec... | 09/05/2006 |
| 7103636 | Methods and apparatus for speculative probing of a remote cluster According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or ... | 09/05/2006 |
| 7089538 | High speed software driven emulator comprised of a plurality of emulation processors with a method to allow memory read/writes without interrupting the emulation A software driven emulator in which the stored emulation program for a processor module is compiled to include a code bit or bits in the emulation instruction step sequence that is decoded as main data memory disable command. Thus, once in each emulation program cyc... | 08/08/2006 |
| 7085897 | Memory management for a symmetric multiprocessor computer system A modular multiprocessor computer system having a plurality of nodes each being in communication with each other via communication links. The plurality of nodes each have local memory and local cache accessible by the other nodes. The plurality of nodes each also ha... | 08/01/2006 |
| 7080238 | Non-blocking, multi-context pipelined processor A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an internally pipelined sub-processor. In one embodiment, the packets are pr... | 07/18/2006 |
| 7080056 | Automatic programming A method for generating a simple kind of computer based artificial consciousness, which means to give a in a computer running invention-pursuant program the capability to act and to know the effects of its actions and to plan further actions consciously. This is rea... | 07/18/2006 |
| 7076597 | Broadcast invalidate scheme A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared d... | 07/11/2006 |
| 7058424 | Method and apparatus for interconnecting wireless and wireline networks A method and apparatus for interconnecting a wireless network and a wireline network include the division of processing functions between a main processor and a plurality of micro-engines. In accordance with an embodiment of the present invention, respective micro-e... | 06/06/2006 |
| 7047370 | Full access to memory interfaces via remote request A technique for enabling a processor to access a memory not directly coupled to the processor. According to the technique, a local processor accesses a remote memory by issuing a memory request that contains an indicator that indicates the request is addressed to th... | 05/16/2006 |
| 7035991 | Surface computer and computing method using the same A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers... | 04/25/2006 |
| 7007121 | Method and apparatus for synchronized buses A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the devices that are part of the transaction. Additionally, the bus freque... | 02/28/2006 |
| 7003633 | Methods and apparatus for managing probe requests According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one... | 02/21/2006 |
| 6996470 | Systems and methods for geophysical imaging using amorphous computational processing Various systems and methods of the present invention provide amorphous computing systems and methods for use thereof. In some cases, the amorphous computing systems include one or more amorphous hardware elements that are programmed under control of a computer proce... | 02/07/2006 |
| 6993639 | Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an ... | 01/31/2006 |
| 6971098 | Method and apparatus for managing transaction requests in a multi-node architecture Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received order... | 11/29/2005 |
| 6950893 | Hybrid switching architecture A hybrid switching module includes a hybrid switching module processor data channel; a hybrid switching module main data channel; an input/output link data channel; a switch coupled to the hybrid switching module processor data channel; and a bridge coupled to the h... | 09/27/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6925548 | Data processor assigning the same operation code to multiple operations A data processor can assign a greater number of operations to instruction codes with shorter length, thereby implementing high performance, high code efficiency and low cost data processor. The data processor is a VLIW (Very Long Instruction Word) system that can ex... | 08/02/2005 |
| 6920519 | System and method for supporting access to multiple I/O hub nodes in a host bridge Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling ro... | 07/19/2005 |
| 6920475 | Communication architecture for distributed computing environment A communication architecture for performing work in a distributed computing environment involves client processes on client nodes sending work requests to a director. The director examines the work requests to determine one or more resources required to perform the ... | 07/19/2005 |
| 6918021 | System of and method for flow control within a tag pipeline A controller comprising a pipeline including a plurality of connected sequential elements wherein a first sequential element is connected to one or more transaction sources; a flow control logic including at least one resource utilization value register; resource al... | 07/12/2005 |
| 6915410 | Compiler synchronized multi-processor programmable logic device with direct transfer of computation results among processors A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description lan... | 07/05/2005 |
| 6836837 | Register addressing There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said ... | 12/28/2004 |
