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| Number | Title | Issue Date |
| 8166280 | Microprocessor for executing byte compiled JAVA code A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a ... | 04/24/2012 |
| 8151091 | Data processing method and system based on pipeline A data processing system and method are disclosed. The system comprises an instruction-fetch stage where an instruction is fetched and a specific instruction is input into decode stage; a decode stage where said specific instruction indicates that contents of a regi... | 04/03/2012 |
| RE43248 | Interoperability with multiple instruction sets Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register fo... | 03/13/2012 |
| 8065504 | Using on-chip and off-chip look-up tables indexed by instruction address to control instruction execution in a processor A microprocessor chip has instruction pipeline circuitry, and instruction classification circuitry that classifies instructions as they are executed into a small number of classes and records a classification code value. An on-chip table has entries corresponding to... | 11/22/2011 |
| 7971032 | System for native code execution A process, apparatus, and system to execute a program in an array of processor nodes that include an agent node and an executor node. A virtual program of tokens of different types represents the program and is provided in a memory. The types include a run type that... | 06/28/2011 |
| 7958335 | Multiple instruction set decoding A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data pro... | 06/07/2011 |
| 7941640 | Secure processors having encoded instructions A processor includes an instruction fetcher, a decoder, and an instruction processor. The instruction fetcher retrieves encoded machine-language instructions. The encoded machine-language instructions are encoded according to a predetermined key assigned only to the... | 05/10/2011 |
| 7941641 | Retargetable instruction decoder for a computer processor According to one embodiment, an instruction decoder for a computer processor includes a fixed instruction decoding portion and at least one look up table having a plurality of random access memory elements. The fixed instruction decoding portion has an input for rec... | 05/10/2011 |
| 7917732 | Microprocessor for executing byte compiled JAVA code A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a ... | 03/29/2011 |
| 7917733 | Instruction code compression using instruction codes with reuse flags An instruction code compression method and an instruction fetch circuit which are capable of reducing both the number of fetches and program codes. A reuse flag is provided in an upper bit group including operational codes, and a lower bit group including operands a... | 03/29/2011 |
| 7873814 | Microcode based hardware translator to support a multitude of processors An apparatus comprising a circuit configured to translate instruction codes of a first instruction set into sequences of instruction codes of a second instruction set that emulate a functionality of the instruction codes of the first instruction set. ... | 01/18/2011 |
| 7856547 | Fast stub and frame technology for virtual machine optimization A method and system for handling of potential unsafe instructions and/or for handling transfers of control in a Virtual Machine, that includes generating a frame composed of pages of analyzed code based on original guest code; identifying instructions within the fra... | 12/21/2010 |
| 7853776 | Handover between software and hardware accelerator A bytecode accelerator which translates stack-based intermediate language (bytecodes) into register-based CPU instructions transfers plural pieces of internal information from a register file of a CPU to the bytecode accelerator by means of an internal transfer bus ... | 12/14/2010 |
| 7836278 | Three operand instruction extension for X86 architecture A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code fi... | 11/16/2010 |
| 7793079 | Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction A method of expanding a conditional instruction having a plurality of operands within a pipeline processor is disclosed. The method identifies the conditional instruction prior to an issue stage and determines if the plurality of operands exceeds a predetermined thr... | 09/07/2010 |
| 7793078 | Multiple instruction set data processing system with conditional branch instructions of a first instruction set and a second instruction set sharing a same instruction encoding A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditio... | 09/07/2010 |
| 7788472 | Instruction encoding within a data processing apparatus having multiple instruction sets A data processing apparatus 2 is provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of ins... | 08/31/2010 |
| 7757067 | Pre-decoding bytecode prefixes selectively incrementing stack machine program counter A processor (e.g., a co-processor) comprising a decoder coupled to a pre-decoder, in which the decoder decodes a current instruction in parallel with the pre-decoder pre-decoding a subsequent instruction. In particular, the pre-decoder examines at least five Bytecod... | 07/13/2010 |
| 7707389 | Multi-ISA instruction fetch unit for a processor, and applications thereof A method and apparatus for recoding one or more instruction sets. An expand instruction and an expandable instruction are read from an instruction cache. A tag compare and way selection unit checks to verify each instruction is a desired instruction. An instruction ... | 04/27/2010 |
| 7664933 | Microcomputer and encoding system for instruction code and CPU A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable a... | 02/16/2010 |
| 7613903 | Data processing device with instruction translator and memory interface device to translate non-native instructions into native instructions for processor A data processing device includes a processor core, and a memory interface portion arranged between the processor core and an external memory mapped into a predetermined external memory space. The memory interface portion includes a fetch circuit for receiving an ad... | 11/03/2009 |
| 7606997 | Method and system for using one or more address bits and an instruction to increase an instruction set A method and system for expanding an instruction set by decoding an instruction located at a particular address using one or more of those address bits in conjunction with the instruction word. ... | 10/20/2009 |
| 7536534 | Processor capable of being switched among a plurality of operating modes, and method of designing said processor A processor has an instruction set A and an instruction set B. A system instruction decoder decodes a system instruction that specifies the operating mode of the processor, the system instruction not being included in either the instruction set A or the instruction ... | 05/19/2009 |
| 7500085 | Identifying code for compilation A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock co... | 03/03/2009 |
| 7493474 | Methods and apparatus for transforming, loading, and executing super-set instructions Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The ... | 02/17/2009 |
| 7478224 | Microprocessor access of operand stack as a register file using native instructions A combined native (RISC or CISC) microprocessor and stack (Java™) machine are constructed so that Java™ VM instructions can be executed in hardware. Most Java™ instructions are executed directly, while more complex Java™ instructions, such as those manipulat... | 01/13/2009 |
| 7447877 | Method and apparatus for converting memory instructions to prefetch operations during a thread switch window A method and apparatus for converting memory instructions to prefetch operations during a thread switch window is disclosed. In one embodiment, memory access instructions that are already inside an instruction pipeline when the current thread is switched out may be ... | 11/04/2008 |
| 7434030 | Processor system having accelerator of Java-type of programming language In a processor system comprising of a processor having an instruction decoder 22, a general register 61 composed of a plurality of register areas and at least one ALU 60, and a Java accelerator 30 for converting a Java bytecode sequence t... | 10/07/2008 |
| 7428630 | Processor adapted to receive different instruction sets A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each exte... | 09/23/2008 |
| 7418580 | Dynamic object-level code transaction for improved performance of a computer A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an executio... | 08/26/2008 |
| 7415599 | Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be performed when the RPT instruction is executed depends upon an initial... | 08/19/2008 |
| 7398373 | System and method for processing complex computer instructions A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction if it was not complex or the jump instructio... | 07/08/2008 |
| 7398372 | Fusing load and alu operations Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops ... | 07/08/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
| 7370159 | Microprocessor having an extended addressable space A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extende... | 05/06/2008 |
| 7370325 | Eager evaluation of tasks in a workflow system An object-focused workflow system for processing a received object in accordance with a declarative workflow specification. The specification includes modules and attributes, where module execution results in the evaluation of attributes, and may include the initiat... | 05/06/2008 |
| 7363476 | Method and apparatus to support an expanded register set According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to acce... | 04/22/2008 |
| 7363620 | Non-linear execution of application program instructions for application program obfuscation Obfuscating an application program comprises reading a first application program, determining an application program instruction location permutation that transforms the first application program into an obfuscated application program having at least one application... | 04/22/2008 |
| 7363475 | Managing registers in a processor to emulate a portion of a stack The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managi... | 04/22/2008 |
| 7360028 | Explicit store-to-instruction-space instruction for self-modifying code and ensuring memory coherence between instruction cache and shared memory using a no-snoop protocol A method and apparatus for performing a store-to-instruction-space instruction are provided. A unique opcode indicates that a data value is to be written to an instruction space in main memory. The instruction is received and executed. After the instruction space is... | 04/15/2008 |
