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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 4949292 | Vector processor for processing recurrent equations at a high speed An improved vector processor for processing a modified recurrent equation: ai =ai-2 ×bi-1 ×bi +bi ×ci-1 +ci, where i is an integer: i=1, 2, 3, . . . , n, at a high speed. The ... | 08/14/1990 |
| 4928238 | Scalar data arithmetic control system for vector arithmetic processor A vector arithmetic processor includes a register file for storing an operand of an instruction supplied from a CPU, at least one pointer register for storing address data for the register file, and a scalar control register for storing a signal represent... | 05/22/1990 |
| 4888679 | Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containi... | 12/19/1989 |
| 4881168 | Vector processor with vector data compression/expansion capability A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfe... | 11/14/1989 |
| 4809171 | Concurrent processing of data operands An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, ... | 02/28/1989 |
| 4791555 | Vector processing unit A functional unit designed with arithmetic pipelining for vector processing is attached to a base data processor from which it receives vector instructions and operands for processing. Stepping of operands and exception indicators through the vector proce... | 12/13/1988 |
| 4760525 | Complex arithmetic vector processor for performing control function, scalar operation, and set-up of vector signal processing instruction The processor is optimized for high-speed processing of large vectors, to fully utilize VHSIC technology, and to implement a signal processor having the highest possible throughput per volume while maintaining flexibility. It includes a 25 MHz embedded 17... | 07/26/1988 |
| 4734877 | Vector processing system A vector processing system including a main storage for storing vector instructions and vector data, an instruction register for holding a vector instruction read out of the main storage, a decoder for decoding the vector instruction held in the instructi... | 03/29/1988 |
| 4636942 | Computer vector multiprocessing control A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to the plurality o... | 01/13/1987 |
| 4400768 | Parallel access computer memory system employing a power-of-two memory modules In a parallel data processing system architecture capable of processing in parallel a plurality of data elements from a linear vector stored in a memory module array having in number a power-of-two memory modules, a high degree of conflict-free access to ... | 08/23/1983 |
| 4378589 | Undirectional looped bus microcomputer architecture A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one o... | 03/29/1983 |
| 4371951 | Apparatus for converting serial input sparse vector format to parallel unpacked format for input to tandem arithmetic logic units Apparatus is disclosed for processing sparse vectors in a tandem or parallel processing environment. Sparce vectors are those vectors stored in memory with their zero-valued operands deleted. They have a corresponding order vector of bits whose state indi... | 02/01/1983 |
