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| Number | Title | Issue Date |
| 5692210 | Image processing apparatus having parallel processors for communicating and performing positional control over plural areas of image data in accordance with designated position instruction An image processing apparatus is composed of an image memory comprising a plurality of memory elements, and a processor unit comprising a plurality of processor elements. By suitably engineering the arrangement of the image memory of memory elements, the ... | 11/25/1997 |
| 5685008 | Computer Processor utilizing logarithmic conversion and method of use thereof A computer processor for performing mathematical operations includes a logarithm converter which generates log values on a data bus, a plurality of processing elements connected to the data bus, an inverse-logarithm converter which receives values from th... | 11/04/1997 |
| 5675823 | Grain structured processing architecture device and a method for processing three dimensional volume element data According to the present invention, a 3D connectivity-conserved grain-structured processing architecture uses connectable massively parallel processors. A 3D grain-structured processing architecture is provided. The 3D links of the grain-structured proces... | 10/07/1997 |
| 5675826 | Image data storage An image data value storage system is described comprising a plurality of tiled memories which are fed with a single set of read addresses from a read address generator. The data stored within each of the tiled memories is offset relative to each other by... | 10/07/1997 |
| 5655137 | Method and apparatus for pre-processing inputs to parallel architecture computers A pre-processing method and pre-processor decompose a first problem belong to a class of linear algebra problems comprising an input sparse symmetric matrix into a suite of sub-problems. The pre-processor generates a suite of signals representing the inf... | 08/05/1997 |
| 5644517 | Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors A matrix transpose method for transposing any size matrix on a 2-dimensional mesh multi-node system with circuit-switched-like routing in the iterative and recursive forms. The matrix transpose method involves a two-level decomposition technique of first ... | 07/01/1997 |
| 5537593 | Method for solving enumerative search problems using message passing on parallel computers A method and apparatus for solving enumerative search, graph search or combinatorial optimization problems using parallel digital processors. Various nodes, representing decision points in the problem, are distributed among a plurality of digital processo... | 07/16/1996 |
| 5504931 | Method and apparatus for comparing data sets A method and apparatus for generating a sequence of displacement vectors and associated minimal error values. The vectors and associated values represent the best match of a current block of elements of a first frame of a signal with one of a plurality of... | 04/02/1996 |
| 5490273 | System of dedicated elementary data processing machines organized in multiple levels and selectively activated to process incoming events A data processing machine comprises a plurality of elementary machines (SUPMS, DEP, ARR, . . . ) disposed in a plurality of levels (level 1, level 2, . . .), and an event presentation device (PTA) responding to the arrival of an event by identifying the l... | 02/06/1996 |
| 5437049 | Reduction processor employing an active associative memory A reduction processor controlled by a program having a structure reduces the structure in a number of reduction steps implementing different kinds of reduction operations. A first order processor of this kind includes an active storage (1, 2) which in tur... | 07/25/1995 |
| 5430886 | Method and apparatus for motion estimation A method and apparatus for generating a sequence of displacement vectors and associated minimal error values. The vectors and-associated values represent the best match of a current block of elements of a first frame of a signal with one of a plurality of... | 07/04/1995 |
| 5426785 | Comparator stack architecture for order statistic filtering of digital imagery This is a circuit design for determining the order statistics of an arbitrary (length and value) string of numbers as the string is acquired. The circuit is intended for use with a system covered by my copending application titled "A High Performance Arch... | 06/20/1995 |
| 5404561 | Clustering and associate processor A clustering and assignment processor (40) for correlating set (12) of two-dimensional data points (14). Clustering is performed by treating each data point (14) as a mass subject to gravitational attraction by other data points (14). The data points (14)... | 04/04/1995 |
| 5377349 | String collating system for searching for character string of arbitrary length within a given distance from reference string A string collating system comprises an input device receiving a reference string and a string to be collated and for generating a coincidence signal when each constituent of the string to be collated is coincident to one character of the reference string,... | 12/27/1994 |
| 5317755 | Systolic array processors for reducing under-utilization of original design parallel-bit processors with digit-serial processors by using maximum common divisor of latency around the loop connection A method of transforming systolic arrays using bit-parallel arithmetic into arrays using digit-serial arithmetic is described. Digit-serial computation is an area-time efficient method of doing high-speed arithmetic calculations, having the advantage thro... | 05/31/1994 |
| 5253363 | Method and apparatus for compiling and implementing state-machine states and outputs for a universal cellular sequential local array A universal sequential logic circuit is constructed from a rectilinear array of elementary logic "cells", with a relatively large number of logic states embodied in a relatively small array. The set of states from a state-machine description of the logic ... | 10/12/1993 |
| 5222237 | Apparatus for aligning the operation of a plurality of processors A method and apparatus are disclosed for aligning a plurality of multi-processors. The apparatus preferably comprises an alignment unit associated with each processor and a logic network for combining the output of the alignment unit and for broadcasting ... | 06/22/1993 |
| 5159690 | Multidimensional cellular data array processing system which separately permutes stored data elements and applies transformation rules to permuted elements A method for coordinating the activity of a plurality of processors in a computing architecture adapted to emulate a physical space, in which spatial locality is reflected in memory organization, including the steps of subdividing the emulated physical sp... | 10/27/1992 |
| 5157778 | Method and apparatus for circuit simulation using parallel processors including memory arrangements and matrix decomposition synchronization A digital data processing system including a plurality of processors processes a program in parallel to load process data into a two-dimensional matrix having a plurality of matrix entries. So that the processors will not have to synchronize loading of pr... | 10/20/1992 |
| 5134711 | Computer with intelligent memory system A programmable memory system that interfaces with a computer's control and data manipulation units, and is capable of performing the manipulation, bookkeeping, and checking that would normally be performed by the computer. The memory system comprises acti... | 07/28/1992 |
| 5019968 | Three-dimensional vector processor A robotics-control processor for performing real-time inverse kinematics and inverse dynamics calculations involving three-dimensional vectors. The processor employs a three-wide register and execution unit architecture, pipelined instructions, and regist... | 05/28/1991 |
| 5018065 | Processor for constrained least squares computations A processor is provided which is suitable for constrained least squares computations. It incorporates a systolic array of boundary, internal, constraint and multiplier cells arranged as triangular and rectangular sub-arrays. The triangular sub-array conta... | 05/21/1991 |
| 4910669 | Binary tree multiprocessor A binary tree multiprocessing array of plural signal processing elements, and having input/output for the array entirely through a root one of the processing elements, includes in each processing element thereof a hardware, pipelined, floating point, mult... | 03/20/1990 |
| 4845610 | Target recognition using string-to-string matching A method for determining whether a perceived target is acceptably close to a model target. The perceived target is first segmented using a relaxation based procedure. Structural features from the perceived target are extracted by producing a compact one-d... | 07/04/1989 |
| 4837739 | Telemetry data processor A telemetry data processor for processing extremely high bandwidth data such as that associated with telemetry from spacecraft. A demultiplexer (1) distributes the data onto several channels (CHl through CHn), each comprising a (preferably split-cycle syn... | 06/06/1989 |
| 4592010 | Memory-programmable controller A memory programmable controller of the multiprocessor type having both word and bit processors is disclosed. The controller has a data memory in which process images of the process being controlled are stored and a user program memory in which a control ... | 05/27/1986 |
| 4224600 | Arrays for parallel pattern recognition In order to perform pictorial pattern recognition at an extremely high data rate, a linear array of photodetectors reads information recorded on photograhic film and the data read is transferred sequentially to an array of microprocessors, converted into ... | 09/23/1980 |
| 4177514 | Graph architecture information processing system An information processing system employing functionally distributed multiple processors has a unique manner of interconnecting and controlling the processors so that the deadlock problem is avoided even though the interconnection of the processors is base... | 12/04/1979 |
