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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 5689661 | Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems An n-dimensional torus network-based parallel computer, n being an integer greater than 1, is folded n times with the results of folding embedded in an n-dimensional layer for connection with an interleave connecting unit. Four-terminal switches or switch... | 11/18/1997 |
| 5680634 | Fixed interconnection network method and apparatus for a modular mixed-resolution, N-dimensional configuration control mechanism A modular, polymorphic network interconnecting a plurality of electronically reconfigurable devices via a modular, polymorphic interconnect, to permit a fixed, physical configuration of operating hardware devices to take on a plurality of logically addres... | 10/21/1997 |
| 5649198 | Mapping calculation units by dividing a calculation model which can be calculated in parallel on an application program This invention aims to perform mapping in a user space without concern for an architecture of a parallel computer and to obtain a high-speed mapping pattern. An N-dimensional model is divided by a user into a plurality of calculation units. The calculatio... | 07/15/1997 |
| 5649106 | Parallel computer with reconstruction of processor clusters A parallel computer having a plurality of cluster buses 2 which are connected to the processor (PE) 1 via the selectors 6. The selectors 6 maintain the same condition until the next instruction is received. In this system, the clusters 11 are reconstructe... | 07/15/1997 |
| 5649179 | Dynamic instruction allocation for a SIMD processor A method and apparatus to dynamically allocate instructions to programmable processing element decoders (78, 79, 80) in a SIMD processor (100) includes a source code instruction (71) for the processor is parsed (1) into components (75, 76, 77) that apply ... | 07/15/1997 |
| 5640586 | Scalable parallel group partitioned diagonal-fold switching tree computing apparatus A parallel computer architecture supporting neural networks utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common... | 06/17/1997 |
| 5619719 | Reduced inter-module circuit path crossovers on circuit boards mounting plural multi-chip modules, through rearranging the north-south-east-west interconnection interfaces of a given module and through selective rotation of each module The number of circuit path crossover points on boards mounting plural connected multichip modules is substantially reduced over the number that would otherwise be required. For 4-sided modules and boards, the modules are arranged on the board in such a wa... | 04/08/1997 |
| 5617575 | Interprocessor priority control system for multivector processor In a multiprocessor computer system, individual vector processors are provided with priority switching signal control circuits, respectively, and a storage control unit incorporating a priority control circuit. Priority bit information is provided for pri... | 04/01/1997 |
| 5617577 | Advanced parallel array processor I/O connection A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used to implement the concept that the port into a node could ... | 04/01/1997 |
| 5613146 | Reconfigurable SIMD/MIMD processor using switch matrix to allow access to a parameter memory by any of the plurality of processors There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A... | 03/18/1997 |
| 5598570 | Efficient data allocation management in multiprocessor computer system The present invention comprises a computer system having a plurality of processors configured in an architecture having at least two subgraphs wherein at least a first subgraph and a second subgraph having the same topology and corresponding processors be... | 01/28/1997 |
| 5594918 | Parallel computer system providing multi-ported intelligent memory A parallel computer system providing multi-ported intelligent memory is formed of a plurality of nodes or cells interconnected to provide a shared memory with processors of the network and their memory providing the network routing and shared memory. Each... | 01/14/1997 |
| 5590345 | Advanced parallel array processor(APAP) A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a n... | 12/31/1996 |
| 5566341 | Image matrix processor for fast multi-dimensional computations An apparatus for multi-dimensional computation which comprises a computation engine, including a plurality of processing modules. The processing modules are configured in parallel and compute respective contributions to a computed multi-dimensional image ... | 10/15/1996 |
| 5475631 | Multiport RAM based multiprocessor Presented is an integrated circuit chip including a random access memory (RAM) array, serial access memory (SAM), an arithmetic logic unit, a bidirectional shift register, and masking circuitry. The arithmetic logic unit, SAM, shift register, and masking ... | 12/12/1995 |
| 5465375 | Multiprocessor system with cascaded modules combining processors through a programmable logic cell array In a multiprocessor data processing system, modules are cascaded by means of intermodule buses. Each module comprises a data processing unit, a first memory, a logic cell array programmable into four input/output interfaces, a second memory and a speciali... | 11/07/1995 |
| 5388214 | Parallel computer system including request distribution network for distributing processing requests to selected sets of processors in parallel A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transf... | 02/07/1995 |
| 5361367 | Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register... | 11/01/1994 |
| 5347639 | Self-parallelizing computer system and method A self-parallelizing computer system and method asynchronously processes execution sequences of instructions in two modes of execution on a set of processing elements which communicate with each other. Each processing element is capable of decoding instru... | 09/13/1994 |
| 5305462 | Mechanism for broadcasting data in a massively parallell array processing system An array processing system including a grid array of processing elements, each of which is surrounded by a group of nearest neighbor processing elements in the grid array, each of said processing elements including an input multiplexer having a multiplexe... | 04/19/1994 |
| 5291611 | Modular signal processing unit A modular signal processing unit capable of being connected in series, palel or combinations thereof, is provided. Each modular unit is a parallel signal processor that receives input data on a plurality of parallel-signal input lines and sends processed... | 03/01/1994 |
| 5280620 | Coupling network for a data processor, including a series connection of a cross-bar switch and an array of silos A coupling network for a data processor is described, including, one or more cross bar switches having inputs and outputs and one or more arrays of silos. A series connection is formed in which these components are alternately arranged in a succession hav... | 01/18/1994 |
| 5265207 | Parallel computer system including arrangement for transferring messages from a source processor to selected ones of a plurality of destination processors and combining responses A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path th... | 11/23/1993 |
| 5218709 | Special purpose parallel computer architecture for real-time control and simulation in robotic applications A Real-time Robotic Controller and Simulator (RRCS) with an MIMD-SIMD parallel architecture for interfacing with an external host computer provides a high degree of parallelism in computation for robotics control and simulation. A host processor receives ... | 06/08/1993 |
| 5212773 | Wormhole communications arrangement for massively parallel processor A parallel processor array is disclosed comprising an array of processor/memories and devices for interconnecting these processor/memories in an n-dimensional pattern having at least 2n nodes through which data may be routed from any processor/... | 05/18/1993 |
| 5203005 | Cell structure for linear array wafer scale integration architecture with capability to open boundary I/O bus without neighbor acknowledgement A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neigh... | 04/13/1993 |
| 5168572 | System for dynamic selection of globally-determined optimal data path A system for choosing a data path through a multi-processor array on a least time and path availability basis. In a preferred embodiment, each processor has an associated path selection element. The element associated with the data source sends out a sign... | 12/01/1992 |
| 5163120 | Second nearest-neighbor communication network for synchronous vector processor, systems and methods A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operati... | 11/10/1992 |
| 5151996 | Multi-dimensional message transfer router A router comprising a plurality of routing nodes interconnected by a plurality of communications links in a multi-dimensional pattern for transferring messages, each message including an address including a series of address digits each associated with on... | 09/29/1992 |
| 5146606 | Systems for interconnecting and configuring plurality of memory elements by control of mode signals An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random proc... | 09/08/1992 |
| 5031139 | Random address system for circuit modules The wafer scale integrated circuit comprises an array of undiced chips or modules, each of which includes a data storing or processing circuit, e.g. a dynamic RAM, and configuration logic. Channels for data and control signals exist between each module an... | 07/09/1991 |
| 5020059 | Reconfigurable signal processor An interconnection scheme among the processing elements ("PEs") of a multiprocessor computing architecture realizes, through PE reconfiguration, both fault tolerance and a wide variety of different processing topologies including binary trees and linear s... | 05/28/1991 |
| 5014189 | Processor array comprising processors connected selectively in series or in parallel A processor array has first through N-th processor. Each of first through (N-1)-th switching devices is connected between preceding and succeeding consecutively numbered ones of the first through the N-th processors. Each processor has at least one proces... | 05/07/1991 |
| 4943909 | Computational origami A processor architecture that permits the realization of any computing function with a regular array of interconnected procssing elements comprising as few as one processing element. The processing element can be as complex as desired. In its minimum form... | 07/24/1990 |
| 4910665 | Distributed processing system including reconfigurable elements A distributed processing system comprising an array of elements each including a plurality of communication ports on which to send or receive data signals is disclosed. Each element further includes means, under program control, for transposing predetermi... | 03/20/1990 |
| 4876644 | Parallel pipelined processor A processor adapted for parallel and/or pipelined interconnection with other like processors. An arithmetic logic unit has associated with it an output FIFO register stack having output data lines capable of parallel connection with the output data lines ... | 10/24/1989 |
| 4876641 | Vlsi data processor containing an array of ICs, each of which is comprised primarily of an array of processing A data processor comprises an array of integrated circuits (ICs), each of which comprises an array of data processing elements (PEs) connected to allow transfer of data. The PEs of the data processor may be organized into array-wide rows and columns with ... | 10/24/1989 |
| 4851995 | Programmable variable-cycle clock circuit for skew-tolerant array processor architecture Using a variable-duration clock circuit, together with programmable duration control to alter the clock waveform within strict rules, permits the programmer to arrange appropriately short durations for short data transfers, and to arrange appropriately lo... | 07/25/1989 |
| 4825359 | Data processing system for array computation A data processing system for array computation including a global memory, a control processor unit for executing microprograms preloaded from the global memory in a local memory of the processor unit, and an array processor unit controlled by the instruct... | 04/25/1989 |
| 4783738 | Adaptive instruction processing by array processor having processor identification and data dependent status registers in each processing element Equipping individual processing elements with an instruction adapter provides an array processor with adaptive spatial-dependent and data-dependent processing capability. The instruction becomes variable, at the processing element level, in response to sp... | 11/08/1988 |
