Quotables
"I watched his countenance closely, to see if he was not deranged ... and I was assured by other senators after he left the room that they had no confidence in it."
U.S. Senator Smith of Indiana ; After seeing Samuel Morse demonstrate the telegraph.
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| Number | Title | Issue Date |
| 6487456 | Method and apparatus for creating a selectable electrical characteristic A device having a variable output electrical characteristic includes first and second output terminals and a number of switching circuits, each switching circuit having two states. One of the states produces a first electrical effect (such as an increased... | 11/26/2002 |
| 6465336 | Circuit and method for providing interconnections among individual integrated circuit chips in a multi-chip module A multi-chip module ("MCM") and methods of operation and manufacture thereof. The MCM includes: (1) a substrate for supporting a plurality of separate integrated circuit (IC) chips thereon, (2) first and second separate IC chips mounted on the substrate, ... | 10/15/2002 |
| 6460128 | Mesh network with method and apparatus for interleaved binary exchange A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent qua... | 10/01/2002 |
| 6460127 | Apparatus and method for signal processing An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cell... | 10/01/2002 |
| 6456620 | Method and apparatus for constructing a latin square matrix for network communication Disclosed is a method for all-to-all personalized exchange for a class of multistage interconnecting networks (MINs). The method is based on a Latin square matrix corresponding to a set of admissible permutations of a multistage interconnecting network. D... | 09/24/2002 |
| 6453406 | Multiprocessor system with fiber optic bus interconnect for interprocessor communications In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sect... | 09/17/2002 |
| 6453344 | Multiprocessor servers with controlled numbered of CPUs A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the total number of available CPUs. Software licensing costs ... | 09/17/2002 |
| 6449667 | Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root A digital computer comprising a plurality of processors interconnected by a network for transferring messages among the processors. At least one processor generates messages of a configuration type. The network comprises a plurality of nodes interconnecte... | 09/10/2002 |
| 6449707 | Information processing unit, information processing structure unit, information processing structure, memory structure unit and semiconductor memory device A data processing unit comprises an input section 1 for inputting first data from the outside, an operation section 2 for operating the first data inputted therefrom, to generate second data, a memory section 3 for storing the second data, an output secti... | 09/10/2002 |
| 6442670 | Data processing system including a shared memory resource circuit A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a ... | 08/27/2002 |
| 6425026 | Distribution, processing, and reconstruction of variable-sized images using multiple processor arrays Selectively distributing a plurality of data items to a plurality of hardware destinations that share a common bus involves, for each one of the data items, determining which of the hardware destinations the data item should be distributed to, wherein at ... | 07/23/2002 |
| 6421772 | Parallel computer with improved access to adjacent processor and memory elements A parallel computer of this invention includes a plurality of memory elements and a plurality of processing elements and each of the processing elements is connected to logically adjacent memory elements. For example, the processing elements which corresp... | 07/16/2002 |
| 6418427 | Online modifications of dimension structures in multidimensional processing A method/operator is disclosed that modifies dimension structures and relations during processing in a multidimensional data cube. The online "blowup" operator disclosed uses one or more hierarchical structures to expand a hypercube in order to reveal int... | 07/09/2002 |
| 6414368 | Microcomputer with high density RAM on single chip A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permi... | 07/02/2002 |
| 6415286 | Computer system and computerized method for partitioning data for parallel processing A computer system splits a data space to partition data between processors or processes. The data space may be split into sub-regions which need not be orthogonal to the axes defined the data space's parameters, using a decision tree. The decision tree ca... | 07/02/2002 |
| 6405299 | Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, w... | 06/11/2002 |
| 6393504 | Dynamic address mapping and redundancy in a modular memory device A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a bus. Each memory module has independent address and command decoders to enable independent operation. Thus each memory module is activated by... | 05/21/2002 |
| 6373484 | Method and system for presenting data structures graphically A computer-implemented method and system for graphically displaying at least two edges extending between common points in a graphical structure. A particular implementation relates to the display of execution paths of a computer program component having m... | 04/16/2002 |
| 6366997 | Methods and apparatus for manarray PE-PE switch control Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and v... | 04/02/2002 |
| 6366999 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based... | 04/02/2002 |
| 6356993 | Dual aspect ratio PE array with no connection switching A single-instruction multiple-data (SIMD) array processor for processing multi-dimensional node meshes that are either elongated or not elongated in at least one coordinate direction. The SIMD array processor includes a plurality of processor arrays inter... | 03/12/2002 |
| 6356992 | Method and apparatus for interleaved exchange in a network mesh A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent qua... | 03/12/2002 |
| 6356994 | Methods and apparatus for instruction addressing in indirect VLIW processors An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-... | 03/12/2002 |
| 6356900 | Online modifications of relations in multidimensional processing A method/operator is disclosed that adjusts measurements during processing in a multidimensional data cube. The online "depth-of-field" operator disclosed varies the density of points in a representation of the multidimensional cube. The operator may be a... | 03/12/2002 |
| 6351798 | Address resolution unit and address resolution method for a multiprocessor system The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and... | 02/26/2002 |
| 6339807 | Multiprocessor system and the bus arbitrating method of the same An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordanc... | 01/15/2002 |
| 6338129 | Manifold array processor An array processor includes processing elements arranged in clusters which are, in turn, combined in a rectangular array. Each cluster is formed of processing elements which preferably communicate with the processing elements of at least two other cluster... | 01/08/2002 |
| 6338106 | I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other... | 01/08/2002 |
| 6334138 | Method for performing alltoall communication in parallel computers The present invention reduces the processing time required for alltoall communications in a parallel computer. When performing alltoall communications in a parallel computer, the number of transfer data units and the number of computers are used as parame... | 12/25/2001 |
| 6324638 | Processor having vector processing capability and method for executing a vector instruction in a processor A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a... | 11/27/2001 |
| 6311311 | Multiple input shift register (MISR) signatures used on architected registers to detect interim functional errors on instruction stream test A method for verifying all intermediate results of a set of architected registers at the end of an instruction stream, even if the final values do not depend on the values of all intermediate results, using a single MISR (Multiple Input Shift Register) to... | 10/30/2001 |
| 6311262 | Apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems The apparatus has a multiplicity of control modules which are assigned to a multiplicity of processing modules for driving purposes. These separate control modules are driven by a superordinate controller and are synchronized by a common synchronization u... | 10/30/2001 |
| 6308279 | Method and apparatus for power mode transition in a multi-thread processor A method and apparatus for power mode transition in a multi-thread processor. A first indication is issued, including a first identifier associated with a first logical processor in a processor, that the first logical processor has entered a power mode. A... | 10/23/2001 |
| 6308251 | Reduced power parallel processor apparatus A parallel processor apparatus capable of reducing the power consumption when converting serial data to parallel data and, at the same time, capable of improving an operating speed, wherein a data input register for converting serial data to parallel data... | 10/23/2001 |
| 6298409 | System for data and interrupt posting for computer devices A system for monitoring issuance of interrupt and transaction commands without involving central processor units of computer systems. The system employs a fabric controller to manage transaction commands among and host devices. The system employs an inter... | 10/02/2001 |
| 6286093 | Multi-bus programmable interconnect architecture A programmable interconnect system having a plurality of PICs connected via a plurality of buses where each bus may have two or more branches connecting the PICs is disclosed. Generally speaking, for a system with N PICs, there can be N-1 different type o... | 09/04/2001 |
| 6279045 | Multimedia interface having a multimedia processor and a field programmable gate array An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or... | 08/21/2001 |
| 6266760 | Intermediate-grain reconfigurable processing device A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way tha... | 07/24/2001 |
| 6263415 | Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networks The present invention provides a new crossbar switch which is implemented by a first plurality of chips. Each chip is completely programmable to couple to every node in the system, e.g., from one node to about one thousand nodes (corresponding to present-... | 07/17/2001 |
| 6256722 | Data processing system including a shared memory resource circuit A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a ... | 07/03/2001 |
