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| Number | Title | Issue Date |
| 5551039 | Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-stan... | 08/27/1996 |
| 5535406 | Virtual processor module including a reconfigurable programmable matrix A virtual processor has a reconfigurable, programmable logic matrix array for processing data in accord with a hardware encoded algorithm, a memory for storing a plurality of hardware configuration files for the programmable logic matrix array, each confi... | 07/09/1996 |
| 5535393 | System for parallel processing that compiles a filed sequence of instructions within an iteration space An improved parallel processing apparatus and method executes an iterative sequence of instructions by arranging the sequence into subtasks and allocating those subtasks to processors. This division and allocation is conducted in such a manner as to minim... | 07/09/1996 |
| 5438682 | Data processing system for rewriting parallel processor output data using a sequential processor A system for performing parallel processing of digital data in order to compute numerical functions and extract characteristic information based on the digital data. After the digital data is processed by the parallel processing portion, a sequential proc... | 08/01/1995 |
| 5367677 | System for iterated generation from an array of records of a posting file with row segments based on column entry value ranges A query processing system for processing queries in connection with a document text base which has entries each identifying a document and a word in the document. The query processing system includes a plurality of processing elements for processing data ... | 11/22/1994 |
| 5325464 | Pyramid learning architecture neurocomputer The Pyramid Learning Architecture Neurocomputer (PLAN) is a scalable stacked pyramid arrangement of processor arrays. There are six processing levels in PLAN consisting of the pyramid base, Level 6, containing N2 SYnapse Processors (SYPs), Leve... | 06/28/1994 |
| 5287466 | Method and apparatus for parallel loads equalizing utilizing instruction sorting by columns based on predicted instruction execution time A parallel processing system wherein the instruction field of each instruction is additionally provided with execution predict count information representative of the number of basic clocks required to execute the instruction, and sort circuits that rearr... | 02/15/1994 |
| 5287532 | Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte A processor array (2) employs an SIMD architecture and includes a number of single-bit processor elements. Each processor element includes an arithmetic unit (ALU) and at least one operand register (Q) for the arithmetic unit (ALU). Each processor element... | 02/15/1994 |
| 4933895 | Cellular array having data dependent processing capabilities A cellular array processor (10) for efficiently performing data dependent processing such as floating point arithmetic functions. One module (84) in the array processor (12) generates a signal applied to bus line (24) when all of the bits in a register (8... | 06/12/1990 |
| 4799152 | Pipeline feedback array sorter with multi-string sort array and merge tree array A feedback array sorter comprising a multi-string sort array having m inputs and outputs and a first buffer memory having m inputs connected to the associated m outputs of said multi-string sort array and q outputs. The buffer includes m×q memory units, ... | 01/17/1989 |
| 4736319 | Interrupt mechanism for multiprocessing system having a plurality of interrupt lines in both a global bus and cell buses A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a d... | 04/05/1988 |
| 4543642 | Data Exchange Subsystem for use in a modular array processor A Data Exchange Subsystem comprising a data bus for transferring data signals, a load for normally maintaining a logical one signal on the data bus, a number of data receivers operatively connected to the data bus for sensing the logic state of the data s... | 09/24/1985 |
| 4215401 | Cellular digital array processor A rectangular digital logic array for performing transformations on data matrices for solving wave equations, image processing problems and the like, includes a plurality of identical cells each having a processing element which receives one of its inputs... | 07/29/1980 |
| 4041461 | Signal analyzer system A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogr... | 08/09/1977 |
| 3936806 | Solid state associative processor organization The invention relates to a unique solid state computer organization. Essentially, the system comprises a plurality of associative arrays wherein each associative array comprises parallel processing apparatus and a solid state memory capable of being acces... | 02/03/1976 |
