Famous Patents
The first commercial microwave oven was nearly 6 feet tall and weighed in at 750 pounds.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 5907855 | Apparatus and method for reducing programming cycles for multistate memory system An apparatus and method for reducing the number of programming states (threshold voltage levels) required to be traversed when programming a multistate memory cell with a given set of data. The invention first determines the average programming state (cor... | 05/25/1999 |
| 5900022 | Apparatus and method for reducing the cache miss penalty in a virtual addressed memory system by using a speculative address generator and an accurate address generator An apparatus and method for reducing the cache miss penalty in a virtual memory system is provided. The virtual memory system includes a processor core which generates virtual addresses and a cache configured to supply information in response to receipt o... | 05/04/1999 |
| 5895500 | Data processing system with reduced look-up table for a function with non-uniform resolution A data processing system with a look-up table means for implementing a transfer function with non-uniform resolution comprises a memory to store a plurality of function data; an input to receive external address words for operating on the memory; and an o... | 04/20/1999 |
| 5893930 | Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer A method for performing predictive translation of a data address in a computer processing system includes organizing a translation lookaside buffer in a set associative manner having each set associated with multiple entries, wherein the multiple entries ... | 04/13/1999 |
| 5893929 | Mutually controlled match-line-to-word-line transfer circuit A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plura... | 04/13/1999 |
| 5893166 | Addressing method and system for sharing a large memory address space using a system space global memory section An addressing method and computer system for sharing a large memory address space using address space within an operating system's virtual address space. The system provides sharing the SSB over many processes without the disadvantages associated with pro... | 04/06/1999 |
| 5875469 | Apparatus and method of snooping processors and look-aside caches The present invention provides a method and apparatus for providing memory coherency among an L1 and an L2 cache memory devices and a main memory device. In an embodiment of the invention, a memory controller generates an address snoop for locating modifi... | 02/23/1999 |
| 5873126 | Memory array based data reorganizer Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from excl... | 02/16/1999 |
| 5852738 | Method and apparatus for dynamically controlling address space allocation A method for managing a memory address space in a memory system, the memory system having multiple block address translation entries, each entry defining a portion of the memory address space, including the steps of determining that a received virtual add... | 12/22/1998 |
| 5845277 | Production of statistically-based network maps A system and method for representing a network according to a hierarchy of views of varying detail. The system models networks as a plurality of interconnected nodes. The display is made more simple by combining network elements (i.e., nodes and connectio... | 12/01/1998 |
| 5835934 | Method and apparatus of low power cache operation with a tag hit enablement A tag hit enable method for low power cache operation is provided which comprises inactivating all output buffers during all cache operations generating a tag hit enable signal, enabling/disabling dataram output buffers with said tag signal, activating on... | 11/10/1998 |
| 5835962 | Parallel access micro-TLB to speed up address translation A memory management unit (MMU) includes a translation lookaside buffer capable of simultaneously servicing three requests supplied to the MMU by an instruction cache and two data caches, respectively. Also, an arbiter selects one of several pending reques... | 11/10/1998 |
| 5829052 | Method and apparatus for managing memory accesses in a multiple multiprocessor cluster system A cluster controller for controlling access to local memory and remote data cache in a multiple cluster computer system. In a multiple cluster computer system, a local memory in a cluster is part of the overall system address space. In order to manage loc... | 10/27/1998 |
| 5802554 | Method and system for reducing memory access latency by providing fine grain direct access to flash memory concurrent with a block transfer therefrom A system and method for reducing access latency to stable storage are described. A technique referred to as fault trickling is used to improve access latency to stable storage such as flash memory. In particular, data requests from a central processing un... | 09/01/1998 |
| 5802602 | Method and apparatus for performing reads of related data from a set-associative cache memory Allocation circuitry for allocating entries within a set-associative cache memory is disclosed. The set-associative cache memory comprises N ways, each way having M entries and corresponding entries in each of the N ways constituting a set of entries. The... | 09/01/1998 |
| 5787493 | Control method and apparatus for direct execution of a program on an external apparatus using a randomly accessible and rewritable memory With the present invention, the page table of the program code non-continuously placed in an external storage device using randomly accessible and rewritable memory is built into an executable sequence in a virtual address space of the CPU according to th... | 07/28/1998 |
| 5784706 | Virtual to logical to physical address translation for distributed memory massively parallel processing systems Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining l... | 07/21/1998 |
| 5784707 | Method and apparatus for managing virtual computer memory with multiple page sizes A computer system having virtual memory that can be mapped using multiple page sizes onto logically addressable physical memory. An intermediate addressing scheme permits the mapping of several non-contiguous small pages in physical memory onto a bigger s... | 07/21/1998 |
| 5778414 | Performance enhancing memory interleaver for data frame processing Disclosed is a frame processing engine for receiving and processing a data frame having a header and a payload, comprising a first memory for receiving at least a portion of the header of the data frame; a second memory for receiving the payload of the da... | 07/07/1998 |
| 5765192 | Method and computer program product to reuse directory search handles A method is disclosed for reusing directory search handles in a manner that minimizes the possibility that a handle allocated for a directory search request that is not yet complete will be reused. This method is implemented by assigning a block of system... | 06/09/1998 |
| 5765209 | Method and apparatus to eliminate redundant mapping in a TLB utilizing variable sized pages The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag. In particular this invention detects conflicts when the pro... | 06/09/1998 |
| 5764944 | Method and apparatus for TLB invalidation mechanism for protective page fault A method and apparatus for modifying protective page fault, which executes TLB table walk when protective page fault occurs in order to modify protective page fault. The method includes the following steps: (1) detecting the occurrence of protective page ... | 06/09/1998 |
| 5758120 | Method and system for increased system memory concurrency in a multi-processor computer system utilizing concurrent access of reference and change bits A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instru... | 05/26/1998 |
| 5734858 | Method and apparatus for simulating banked memory as a linear address space A method and apparatus for providing access to a banked peripheral memory via a contiguous linear address space. The present invention provides a linear address space having a present region that is mapped to a host memory region of a computer system. The... | 03/31/1998 |
| 5732285 | Method and apparatus for consolidated buffer handling for computer device input/output A computer has a device driver and an operating system that call a consolidated buffer service routine to coordinate the transfer of data between a main memory and an external device. The consolidated buffer service routine includes a memory preparation s... | 03/24/1998 |
| 5729711 | Data driven information processing system using address translation table to keep coherent cache and main memories and permitting parallel readings and writings The system includes a data driven processor, a main memory, a cache memory and a memory access unit for accessing the cache memory, the main memory or both and for maintaining the contents of the cache memory in coherence with the contents of the main mem... | 03/17/1998 |
| 5712998 | Fast fully associative translation lookaside buffer with the ability to store and manage information pertaining to at least two different page sizes A fast, fully associative translation lookaside buffer (TLB) with the ability to store and manage information pertaining to at least two different page sizes is described. The TLB utilizes a tag array with tag lines and a data array with corresponding dat... | 01/27/1998 |
| 5699539 | Virtual memory management system and method using data compression A virtual memory system and method enable a computer system to use a virtual memory address space larger than the size of physical primary memory while swapping few, if any, pages out to secondary memory. Primary memory is divided into a work space, used ... | 12/16/1997 |
| 5696925 | Memory management unit with address translation function Memory management unit with address translation function improves the translation speed for virtual addresses and minimizes the deviation in response time. The memory management unit translates partially and entirely the virtual address into an physical a... | 12/09/1997 |
| 5684974 | Method and apparatus for controlling reconfiguration of storage-device memory areas An apparatus and method for controlling the reconfiguration of the physical storage area in a real storage device employed by an information processing system. The invention includes an address reconfiguration array having a plurality of storage blocks wh... | 11/04/1997 |
| 5680565 | Method and apparatus for performing page table walks in a microprocessor capable of processing speculative instructions A page table walk is performed in response to a data translation lookaside buffer miss based on a speculative memory instruction. In the event of a data translation lookaside buffer miss, a page miss handler determines whether the memory micro-instruction... | 10/21/1997 |
| 5664144 | System and method for FBA formatted disk mapping and variable-length CKD formatted data record retrieval An apparatus and method for disk mapping and data retrieval includes a data storage medium on which has been stored a plurality of data records. Each record includes at least a record identification portion, for uniquely identifying each record from among... | 09/02/1997 |
| 5664217 | Method of avoiding physical I/O via caching with prioritized LRU management A method of caching I/O requests permits caching in the MVS environment independent of the access method protocol used to initiate an I/O request (e.g., QSAM, VSAM, Media Manager). In addition, objects can be user-prioritized for residence in the cache.... | 09/02/1997 |
| 5649139 | Method and apparatus for virtual memory mapping and transaction management in an object-oriented database system An apparatus and method are provided for virtual memory mapping and transaction management in an object-oriented database system having permanent storage for storing data in at least one database, at least one cache memory for temporarily storing data, an... | 07/15/1997 |
| 5634009 | Network data collection method and apparatus Disclosed are a method and apparatus for collecting network data from a computer network. Control structures are created for groups of data to be collected. The control structures are then associated with corresponding tables for storing the data. Differe... | 05/27/1997 |
| 5630087 | Apparatus and method for efficient sharing of virtual memory translations A method and apparatus to share virtual memory translations in a computer is described. The apparatus includes an operating system that runs in conjunction with a central processing unit. The operating system is programmed to include an address identifica... | 05/13/1997 |
| 5627992 | Organization of an integrated cache unit for flexible usage in supporting microprocessor operations A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclus... | 05/06/1997 |
| 5615392 | Method and apparatus for consolidated buffer handling for computer device input/output A computer has a device driver and an operating system that call a consolidated buffer service routine to coordinate the transfer of data between a main memory and an external device. The consolidated buffer service routine includes a memory preparation s... | 03/25/1997 |
| 5596735 | Circuit and method for addressing segment descriptor tables In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local b... | 01/21/1997 |
| 5537587 | File record maintenance in a data processing system by synchronization of menus with corresponding data files A program allows a user to know instantly which data files have not been updated, which data files or menu items may have been incorrectly named and which data files have no corresponding references on the menus. The program matches a series of menus for ... | 07/16/1996 |
