Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 5526502 | Memory interface A memory interface device capable of memory accessing suitable for video image signal processing and memory accessing designating an arbitrary address. The interface includes an input scrambler for rewriting the generation number of an input data packet u... | 06/11/1996 |
| 5522027 | External interface for a high performance graphics adapter allowing for graphics compatibility An interface for a high-performance graphics adapter is provided. A computer system includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application computer prog... | 05/28/1996 |
| 5509137 | Store processing method in a pipelined cache memory A cache memory apparatus and microprocessor therewith has a first address register for a tag memory and a second address register for a data memory, a tag entry decoder and a data entry decoder. Lower order bits of the contents stored in the first address... | 04/16/1996 |
| 5500948 | Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache A data processing system comprised of a memory, a translation lookaside buffer (TLB) providing access to the memory, and an instruction cache connected to the memory. A two entry translation write buffer (TWB) has a first entry that is a first logical reg... | 03/19/1996 |
| 5479627 | Virtual address to physical address translation cache that supports multiple page sizes A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page ... | 12/26/1995 |
| 5471599 | Partitioning of virtual addressing memory A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performan... | 11/28/1995 |
| 5442766 | Method and system for distributed instruction address translation in a multiscalar data processing system A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher un... | 08/15/1995 |
| 5438663 | External interface for a high performance graphics adapter allowing for graphics compatibility An interface for a high-performance graphics adapter is provided. In a computer system which includes a host processor, a coprocessor in the form of a graphics system processor, and memory addressable by both the host and coprocessors. An application comp... | 08/01/1995 |
| 5437016 | Apparatus and method for translating logical addresses for virtual machines An absolute address translated from a logical address input by a user program by an address translation circuit and a prefix translation circuit, is compared with contents of a virtual processor prefix register. On the basis of the comparison result, a mu... | 07/25/1995 |
| 5430888 | Pipeline utilizing an integral cache for transferring data to and from a register A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. ... | 07/04/1995 |
| 5428757 | Method for reducing translation look aside buffer purges in a multitasking system A process for reducing translation look-aside buffer (TLB) purge overhead does so by purging the TLB only when required to avoid invalid entries. The translation look-aside buffer (TLB) contains virtual to real mappings for a particular address space. Ope... | 06/27/1995 |
| 5392410 | History table for prediction of virtual address translation for cache access A 1-dimensional history table, which has been named a TLBLAT, is used to predict some or all of the real address bits that correspond to (i.e., translate from) any given virtual page address in order to provisionally access a real address based cache. The... | 02/21/1995 |
| 5265220 | Address control device for effectively controlling an address storing operation even when a request is subsequently cancelled In an address control device operable in response to an input virtual address signal to control an access operation to a memory section, an address storing operation is started by an address conversion control section (22) when no real address part is sto... | 11/23/1993 |
| 5247673 | Multiprocessor system having distributed shared resources and dynamic global data replication A multiprocessor system has distributed shared resources and dynamic global data replication in which a plurality of processors communicate each with the other through a system bus. Each CPU is provided with a local memory for storing data used locally an... | 09/21/1993 |
| 5155834 | Reference and change table storage system for virtual memory data processing system having a plurality of processors accessing common memory In a multi-processor virtual memory system 10 a Reference and Change Table (RCT) 36 is located upon a Memory Control Unit (MCU) 25. The RCT 36 is responsive to accesses to any of the Memory Modules (MMs) 24-26 and generates and maintains status bits indic... | 10/13/1992 |
| 5148538 | Translation look ahead based cache access This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the... | 09/15/1992 |
| 5060137 | Explicit instructions for control of translation lookaside buffers Explicit instructions are provided that enable software to directly control insertion of information into a translation lookaside buffer (TLB). A first pair of instructions enable information to be inserted into a data TLB and a second pair of instruction... | 10/22/1991 |
| 4849881 | Data processing unit with a TLB purge function A data processing unit with a TLB purge function has an address counter in which TLB purge data including an address space identifier, segment number, and page number are held. In TLB purge processing, A TLB is indexed by the upper data from the counter s... | 07/18/1989 |
| 4577274 | Demand paging scheme for a multi-ATB shared memory processing system Disclosed is a demand paging scheme for a shared memory processing system that uses paged virtual memory addressing and includes a plurality of address translation buffers (ATBs). Page frames of main memory that hold pages being considered for swapping fr... | 03/18/1986 |
| 4464713 | Method and apparatus for converting addresses of a backing store having addressable data storage devices for accessing a cache attached to the backing store A cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system ... | 08/07/1984 |
