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| Number | Title | Issue Date |
| 8190852 | Virtualization controller and data transfer control method System for controlling data transfer between a host system and storage devices. A virtualization controller implements the data transfer and includes first ports for connection with the storage devices, a second port for connection with the host system, a processor,... | 05/29/2012 |
| 8151084 | Using address and non-address information for improved index generation for cache memories Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information a... | 04/03/2012 |
| 8103850 | Dynamic translation in the presence of intermixed code and data A system for translating software in a first format into a second format includes a memory containing the software in the first format and an emulator coupled to the memory configured to translate the software from the first format to the second format. The system a... | 01/24/2012 |
| 7930514 | Method, system, and computer program product for implementing a dual-addressable cache A method, system, and computer program product for implementing a dual-addressable cache is provided. The method includes adding fields for indirect indices to each congruence class provided in a cache directory. The cache directory is indexed by primary addresses. ... | 04/19/2011 |
| 7925859 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information... | 04/12/2011 |
| 7913058 | System and method for identifying TLB entries associated with a physical address of a specified range A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB e... | 03/22/2011 |
| 7913057 | Translation lookaside buffer checkpoint system A system that, at a process checkpoint, pauses the process to copy the system state for the process and then copies pages of the process in memory to disk storage while the process continues to run. When a write to a page by the process is to occur that requires a t... | 03/22/2011 |
| 7849112 | Using a file handle for associating the file with a tree quota in a file server To avoid the need for storing a tree quota identifier attribute for every file in a quota tree, a tree quota identifier is included in the file handle returned by the file server to a client in response to a directory lookup request. The file server discovers that t... | 12/07/2010 |
| 7721067 | Translation lookaside buffer manipulation A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that informa... | 05/18/2010 |
| 7558939 | Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information... | 07/07/2009 |
| 7543133 | Latency tolerant distributed shared memory multiprocessor computer A computer system having low memory access latency. In one embodiment, the computer system includes a network and one or more processing nodes connected via the network, wherein each processing node includes a plurality of processors and a shared memory connected to... | 06/02/2009 |
| 7516297 | Memory management Systems, methods, and devices are provided for memory management. One method embodiment includes providing an operating system capable of supporting variable page sizes. The method includes providing a virtual memory address, translating the virtual memory address t... | 04/07/2009 |
| 7447869 | Method and apparatus for fragment processing in a virtual memory system A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page... | 11/04/2008 |
| 7434100 | Systems and methods for replicating virtual memory on a host computer and debugging using replicated memory Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having... | 10/07/2008 |
| 7426625 | Data processing system and computer program product for support of system memory addresses with holes A method, computer program product, and a data processing system for supporting memory addresses with holes is provided. A first physical address range allocated for system memory for an operating system run by a processor configured to support logical partitioning ... | 09/16/2008 |
| 7412585 | Method for controlling disk drive using an address translation table Embodiments of the invention achieve data write in an appending manner by conversion from a logical block address to a physical block address in a HDD that has only one storage device and does not have a large-scale cache memory. In one embodiment, a check is made a... | 08/12/2008 |
| 7409524 | System and method for responding to TLB misses The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be util... | 08/05/2008 |
| 7409494 | Extension of write anywhere file system layout A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggrega... | 08/05/2008 |
| 7395405 | Method and apparatus for supporting address translation in a virtual machine environment In one embodiment, a method includes receiving control transitioned from a virtual machine (VM) due to a privileged event pertaining to a translation-lookaside buffer (TLB), and determining which entries in a guest translation data structure were modified by the VM.... | 07/01/2008 |
| 7389400 | Apparatus and method for selectively invalidating entries in an address translation cache An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may... | 06/17/2008 |
| 7389402 | Microprocessor including a configurable translation lookaside buffer A translation lookaside buffer may include control functionality coupled to a first storage and a second storage. The first storage includes a first plurality of entries for storing address translations corresponding to a plurality of page sizes. The second storage ... | 06/17/2008 |
| 7386669 | System and method of improving task switching and page translation performance utilizing a multilevel translation lookaside buffer A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache m... | 06/10/2008 |
| 7386614 | Method allowing persistent links to web-pages A system that enables creation of URL addresses in which the path information is partially or entirely symbolic. The symbolic path information is maintained even after the physical path information is altered, whereby users do not have to learn or provide constantly... | 06/10/2008 |
| 7383415 | Hardware demapping of TLBs shared by multiple threads In one embodiment, a processor comprising at least one translation lookaside buffer (TLB) and a control unit coupled to the TLB. The control unit is configured to track whether or not at least one update to the TLB is pending for at least one of a plurality of stran... | 06/03/2008 |
| 7380096 | System and method for identifying TLB entries associated with a physical address of a specified range A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB e... | 05/27/2008 |
| 7376807 | Data processing system having address translation bypass and method therefor In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and conver... | 05/20/2008 |
| 7373479 | Method to allow PCI host bridge (PHB) to handle pre-fetch read transactions on the PCI bus which access system memory through translation control entry (TCE) table A method, system, and computer instructions for providing valid translation entries in the TCE table for all supported DMA addresses to prevent the occurrence of system errors due to prefetching. The mechanism of the present invention reserves a page in system memor... | 05/13/2008 |
| 7373478 | Information processing apparatus and software pre-fetch control method In an information processing apparatus (10) that includes a cache memory (560) formed from at least one hierarchy, and a pre-fetch command that speculatively transfers data or a command from a main storage (30) to the cache memory, a cache contr... | 05/13/2008 |
| 7370151 | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array ... | 05/06/2008 |
| 7370174 | Method, system, and program for addressing pages of memory by an I/O device Provided are a method, system, and program for translating virtual addresses of memory locations within pages of different sizes. In one embodiment, a translation entry containing a physical address is stored in a data structure table for each page. Each virtual add... | 05/06/2008 |
| 7370160 | Virtualizing memory type A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory ... | 05/06/2008 |
| 7370177 | Mechanism for avoiding check stops in speculative accesses while operating in real mode A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding... | 05/06/2008 |
| 7366848 | Reducing resource consumption by ineffective write operations in a shared memory system In a shared memory system, ineffective write operations (“dead stores”) can be handled in a manner to reduce unnecessary consumption of resources. In a shared memory system, when a non-owning processing unit requests data from a shared memory location owned by a... | 04/29/2008 |
| 7366869 | Method and system for optimizing translation lookaside buffer entries A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic c... | 04/29/2008 |
| 7363491 | Resource management in security enhanced processors A processor divides resources into secure resources and non-secure resources. Virtual-to-physical address translation page tables may be stored in either secure or non-secure memory. ... | 04/22/2008 |
| 7360056 | Multi-node system in which global address generated by processing subsystem includes global to local translation information A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated wi... | 04/15/2008 |
| 7356026 | Node translation and protection in a clustered multiprocessor system A method of node translation for communicating over virtual channels in a clustered multiprocessor system using connection descriptors (CDs), which specify the endpoint nodes for virtual connections. The system includes a local processing element node, a remote proc... | 04/08/2008 |
| 7353360 | Method for maximizing page locality A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a corresponding memory hierarchy wherein each memory hierarchy has a table of pages... | 04/01/2008 |
| 7350019 | Content addressable memory device capable of being used in cascaded fashion The configuration of a CAM device can be set in various manners depending on a system in which CAM having different configurations is needed. The CAM device includes a CAM array including a plurality of physical banks, a logical bank-physical bank converter for sett... | 03/25/2008 |
| 7350053 | Software accessible fast VA to PA translation A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address tra... | 03/25/2008 |
