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| Number | Title | Issue Date |
| 7243169 | Method, system and program for oscillation control of an internal process of a computer program A method for reducing oscillations of an output value associated with a program to be operatively coupled to a data processing system. The program having an internal process configured to read an input value provided by the program, the input value adjusting a perfo... | 07/10/2007 |
| 7243208 | Data processor and IP module for data processor In performing address translation from a virtual address space to a physical address space, when the virtual address space is divided into an area (P0), which is subjected to the address translation by TLB, and areas (P1 and P2), which are fixed... | 07/10/2007 |
| 7243245 | Method and system for performing automatic startup application launch elimination A method and system for controlling a startup sequence in a computer system is disclosed. The method and system include monitoring at least one aspect of a plurality of startup applications launched during the startup sequence. The method and system further include ... | 07/10/2007 |
| 7240143 | Data access and address translation for retrieval of data amongst multiple interconnected access nodes A low-latency storage memory system is built from multiple memory units such as high-density random access memory. Multiple access ports provide access to memory units and send the resultant data out interface ports. The memory units communicate with the access port... | 07/03/2007 |
| 7240158 | System and method for caching results In certain aspects, the invention features a system and method for caching results, including receiving a job for computation by a distributed computing system having one or more node computing devices in communication with a cache, processing, on one of the node co... | 07/03/2007 |
| 7240057 | System and method for implementing journaling in a multi-node environment A system and method are disclosed for providing journaling in a computer environment. An embodiment of the present invention comprises providing a first node and a second node; providing a journal wherein the journal is accessible by the first node and the second no... | 07/03/2007 |
| 7240178 | Non-volatile memory and non-volatile memory data rewriting method A nonvolatile memory and a data rewriting method of the nonvolatile memory that can readily detect a state of operation at a time of a system failure due to a power failure or the like and quickly and reliably restore the nonvolatile memory to a normal storage state... | 07/03/2007 |
| 7240179 | System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is ina... | 07/03/2007 |
| 7237046 | Data storage device with full access by all users A peripheral device of a host computer includes a microcontroller and two virtual devices. The first virtual device passes, to the microcontroller, commands of a first command set from any user of the host computer and preferably also commands of a second command se... | 06/26/2007 |
| 7236987 | Systems and methods for providing a storage virtualization environment A storage virtualization environment is provided that includes a system for providing one or more virtual volumes. The system may include a host system and a set of storage devices, each of which includes physical block addresses that stores data. Further, the syste... | 06/26/2007 |
| 7237237 | Designating an object for destruction A method for controlling disposition of a candidate object in an object-oriented programming environment is disclosed. The method may include the step of determining the number of cyclic paths that include the candidate object in the object-oriented programming envi... | 06/26/2007 |
| 7237102 | Methods and apparatus for configuring hardware resources in a pre-boot environment without requiring a system reset Methods and apparatus for configuring a hardware device in a pre-boot environment are disclosed. For example, a configuration manager is provided for use in a computer having a processor. The example configuration manager includes an interrupt monitoring agent in co... | 06/26/2007 |
| 7234038 | Page mapping cookies A method for managing virtual memory including placing a first virtual memory page in a physical memory page to create a virtual-to-physical memory mapping, associating a first page mapping cookie value with the virtual-to-physical memory mapping, determining whethe... | 06/19/2007 |
| 7234039 | Method, system, and apparatus for determining the physical memory address of an allocated and locked memory buffer Methods and systems are provided for determining the physical address of an allocated and locked memory buffer. An application program may request the allocation of a memory buffer. A virtual memory address for the memory buffer is then returned. The virtual memory ... | 06/19/2007 |
| 7234006 | Generalized addressing scheme for remote direct memory access enabled devices An apparatus accesses a resource in a computer system. The resource is accessible at a physical memory address (49) of the computer system. The apparatus comprises means for determining at least one identity parameter for the resource and means for storing a ... | 06/19/2007 |
| 7234037 | Memory mapped Input/Output operations A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with... | 06/19/2007 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 06/19/2007 |
| 7228400 | Control of multiply mapped memory locations A technique to manage multiple-mapped memory and to selectively execute at least a portion of a process from either an unprotected function or a protected function. The process contains memory that is multiple-mapped to both an unprotected memory region and to a pro... | 06/05/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7227994 | Method and apparatus for imbedded pattern recognition using dual alternating pointers A method and apparatus for finding a reference pattern (RP) with K elements imbedded in an input pattern IP with repeating substrings uses dual pointers to point to elements in the RP to compare with input elements sequentially clocked from the IP. The dual pointers... | 06/05/2007 |
| 7228435 | Program executing method in service system and program executing apparatus for the same A program executing apparatus includes a first storage section which stores data permitted to be leaked out; a second storage section which stores secret data of a user; a communication section which can communicate with an external unit; a program storage section w... | 06/05/2007 |
| 7225316 | Memory mapping apparatus, systems, and methods An apparatus and a system, as well as a method and article, may operate to map, by an operating system, a range of virtual addresses to a range of physical addresses, wherein a subset of the range of virtual addresses is identity-mapped to a subset of the range of p... | 05/29/2007 |
| 7225317 | System and method for managing storage networks and for managing scalability of volumes in such a network This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with the new architecture. A method for handling errors is included in anot... | 05/29/2007 |
| 7222136 | Communicating data dictionary information of database objects through a redo stream A system, method, and computer program product communicate data dictionary information of database objects through a redo stream in the form of metadata, which provides the association between the internal numbers used by a database schema to identify database objec... | 05/22/2007 |
| 7219210 | Memory allocation to multiple computing units Memory allocation to multiple computing units is disclosed. A static offset for each computing unit is determined, and a portion of memory is allocated for each computing unit, and remapped into a contiguous logical region that is addressable by a pointer plus the s... | 05/15/2007 |
| 7219202 | Cluster storage system and replication creation method thereof In a storage system having a plurality of control units each connected with a plurality of disk units, it is provided that a replication is created in the volume of the disk units connected to different control units. The replication creation unit of a given control... | 05/15/2007 |
| 7218407 | Image printing system A capture command in the AV/C protocol of the IEEE 1394 standard is set as follows. The quantity of data to be transmitted (data_size), the number of pixels in the X-direction (image_size_x) and the number of pixels in the Y-direction (image_size_y) are all s... | 05/15/2007 |
| 7219369 | Internal memory type tamper resistant microprocessor with secret protection function In an inner memory type tamper resistant microprocessor, a requested secret protection attribute requested for each access target memory page by a task is set and stored exclusively from other tasks, at a time of reading a program into memory pages and executing the... | 05/15/2007 |
| 7216345 | Method and apparatus for protectively operating a data/information processing device A privilege level re-mapping mechanism is provided to a processor to re-map privilege levels. The re-mapping mechanism is placed in between the control registers and the privilege checking circuitry, to enable the re-mapping to be dynamically performed in real time ... | 05/08/2007 |
| 7213248 | High speed promotion mechanism suitable for lock acquisition in a multiprocessor data processing system A multiprocessor data processing system includes a plurality of processors coupled to an interconnect and to a global promotion facility containing at least one promotion bit field. A first processor executes a high speed instruction sequence including a load-type i... | 05/01/2007 |
| 7213098 | Computer system and method providing a memory buffer for use with native and platform-independent software code The present invention relates to computer systems and methods for providing a memory buffer for use with native and platform-independent software code. In a particular embodiment, the method includes providing a first software program compiled to platform-ind... | 05/01/2007 |
| 7213108 | Information processing apparatus and method, storage medium, program and imaging apparatus An instruction virtual address space includes only virtual addresses corresponding to physical addresses of address areas of a physical address space storing pages of only instructions. A data virtual address space includes only virtual addresses corresponding to ph... | 05/01/2007 |
| 7213125 | Method for patching virtually aliased pages by a virtual-machine monitor Various embodiments of the present invention are directed to methods by which a virtual-machine monitor can introduce branch instructions, in order to emulate privileged and other instructions on behalf of a guest operating system, into guest-operating-system code r... | 05/01/2007 |
| 7213041 | Saving and restoring an interlocking trees datastore A tree-based datastore comprising a forest of interconnected trees that can be generated and/or accessed may require specialized saving and restoring processes to ensure that all the links are properly maintained whether it will be restored in full or in part. A pre... | 05/01/2007 |
| 7209989 | Transfer acknowledgement mechanism for an MSL architecture Method and apparatus relating to an acknowledgement mechanism in an interconnected subsystem architecture. After a data message is transmitted, the transmitting device may transmit an acknowledge message on a channel undefined by the inter-subsystem communication pr... | 04/24/2007 |
| 7209994 | Processor that maintains virtual interrupt state and injects virtual interrupts into virtual machine guests In one embodiment, a processor comprises one or more registers and a control unit. The registers are configured to store interrupt state describing a virtual interrupt. The control unit is configured to initiate the virtual interrupt responsive to the interrupt stat... | 04/24/2007 |
| 7209489 | Arrangement in a channel adapter for servicing work notifications based on link layer virtual lane processing A host channel adapter is configured for servicing received work notifications based on identifying the work notifications associated with the virtual lanes (VL) having a prescribed ordering position identified by the link layer operations. The host channel adapter,... | 04/24/2007 |
| 7210127 | Methods and apparatus for executing instructions in parallel A system, method and apparatus for executing instructions in parallel identify a set of traces within a segment of code, such as Java bytecode. Each trace represents a sequence of instructions within the segment of code that are execution structure dependent, such a... | 04/24/2007 |
| 7206915 | Virtual space manager for computer having a physical address extension feature A physical address extension feature maps multiple virtual memory spaces to an extended physical memory. A virtual space manager dynamically allocates pages of the physical memory to respective virtual spaces. The virtual space manager responds to a request from an ... | 04/17/2007 |
| 7206906 | Physical address mapping framework Provided is a method and apparatus for registering requests to access physical memory in a physical address mapping framework. Specifically, a device can register in the physical address mapping framework before accessing physical memory, thus permitting an operatin... | 04/17/2007 |
